def pack(self, buff, offs):
#MAC and VLAN ID
mac64 = int(self.MAC.translate(self.MAC.maketrans('', '', ':.- ')), 16)
#print('mac64_TX: ', hex(mac64) )
#REG1
REG1 = mac64 & 0xFFFFFFFF
#REG2
REG2 = _VAL2FLD(mac64 >> 32, ItemMAC_REG2_MAC_Hi16_Pos, ItemMAC_REG2_MAC_Hi16_Msk) \
| _VAL2FLD(self.vlanID, ItemMAC_REG2_VlanID_Pos, ItemMAC_REG2_VlanID_Msk)
#PACK to Buff
struct.pack_into("LL", buff, offs, REG1, REG2)
def pack(self, buff, offs):
mac64 = int(self.MAC.translate(self.MAC.maketrans('', '', ':.- ')), 16)
# #print('mac64_TX: ', hex(mac64) )
REG1 = (mac64 >> 16) & 0xFFFFFFFF
REG2 = _VAL2FLD(mac64, ItemMAC_R2_MAC_Lo16_Pos,
ItemMAC_R2_MAC_Lo16_Msk)
REG3 = _VAL2FLD(self.Age, ItemMAC_R2_AGE_Pos, ItemMAC_R2_AGE_Msk) \
| _VAL2FLD(self.Port, ItemMAC_R2_PORT_Pos, ItemMAC_R2_PORT_Msk) \
| ItemMAC_R2_ACT_Msk
hashAddr = (self.Hash << VV3_HashToAddr_Pos) | (self.HashInd
& VV3_HashInd_Mask)
struct.pack_into(">LH", buff, offs, REG1, REG2)
struct.pack_into("HH", buff, offs + 6, REG3, hashAddr)
def pack(self, buff, offs):
R0 = self.key.vlanID & ItemVLAN_REG1_VlanID_Msk
R1 = _VAL2FLD(self.forwPorts, EntryVLAN_REG1_ForwPorts_Pos, EntryVLAN_REG1_ForwPorts_Msk) \
| _VAL2FLD(self.untaggedPorts, EntryVLAN_REG1_UntagPortsLo_Pos, EntryVLAN_REG1_UntagPortsLo_Msk)
R2 = _VAL2FLD(self.untaggedPorts >> EntryVLAN_REG2_UntagPortsHi_Offs, EntryVLAN_REG2_UntagPortsHi_Pos, EntryVLAN_REG2_UntagPortsHi_Msk) \
| _VAL2FLD(self.UCastHitAct, EntryVLAN_REG2_UCastHit_Pos, EntryVLAN_REG2_UCastHit_Msk) \
| _VAL2FLD(self.MCastHitAct, EntryVLAN_REG2_MCastHit_Pos, EntryVLAN_REG2_MCastHit_Msk) \
| _VAL2FLD(self.UCastMissAct, EntryVLAN_REG2_UCastMiss_Pos, EntryVLAN_REG2_UCastMiss_Msk) \
| _VAL2FLD(self.MCastMissAct, EntryVLAN_REG2_MCastMiss_Pos, EntryVLAN_REG2_MCastMiss_Msk) \
| _VAL2FLD(self.MSTPAct, EntryVLAN_REG2_MSTP_Pos, EntryVLAN_REG2_MSTP_Msk)
#struct.pack_into("HLL", buff, offs, R0, R1, R2)
self.key.pack(buff, offs)
struct.pack_into("LL", buff, offs + KX028_KeyVLAN.packLen, R1, R2)
def pack(self, buff, offs):
REG3 = _VAL2FLD(self.forwPorts, MAC_ENTRY_FWD_PORT_LIST_Pos, MAC_ENTRY_FWD_PORT_LIST_Msk) \
| _VAL2FLD(self.tc, MAC_ENTRY_TC_Pos, MAC_ENTRY_TC_Msk) \
| _VAL2FLD(self.action, MAC_ENTRY_FWD_ACT_Pos, MAC_ENTRY_FWD_ACT_Msk) \
| _VAL2FLD(self.cutThrough, MAC_ENTRY_CUT_THROUGH_Pos, MAC_ENTRY_CUT_THROUGH_Msk) \
| _VAL2FLD(self.isFresh, MAC_ENTRY_FRESH_Pos, MAC_ENTRY_FRESH_Msk) \
| _VAL2FLD(self.isStatic, MAC_ENTRY_STATIC_Pos, MAC_ENTRY_STATIC_Msk) \
#PACK to Buff
self.key.pack(buff, offs)
struct.pack_into("L", buff, offs + KX028_KeyMAC.packLen, REG3)
def pack(self, buff, offs):
#REG1
REG1 = _VAL2FLD(self.vlanID, ItemVLAN_REG1_VlanID_Pos, ItemVLAN_REG1_VlanID_Msk) \
| _VAL2FLD(self.forwPorts, ItemVLAN_REG1_ForwPortsLo_Pos, ItemVLAN_REG1_ForwPortsLo_Msk)
#REG2
REG2 = _VAL2FLD(self.forwPorts >> ItemVLAN_REG2_ForwPortsHi_Offs, ItemVLAN_REG2_ForwPortsHi_Pos, ItemVLAN_REG2_ForwPortsHi_Msk) \
| _VAL2FLD(self.untaggedPorts, ItemVLAN_REG2_UntagPorts_Pos, ItemVLAN_REG2_UntagPorts_Msk) \
| _VAL2FLD(self.UCastHitAct, ItemVLAN_REG2_UCastHit_Pos, ItemVLAN_REG2_UCastHit_Msk) \
| _VAL2FLD(self.MCastHitAct, ItemVLAN_REG2_MCastHit_Pos, ItemVLAN_REG2_MCastHit_Msk) \
| _VAL2FLD(self.UCastMissAct, ItemVLAN_REG2_UCastMiss_Pos, ItemVLAN_REG2_UCastMiss_Msk) \
| _VAL2FLD(self.MCastMissAct, ItemVLAN_REG2_MCastMissLo_Pos, ItemVLAN_REG2_MCastMissLo_Msk)
#REG3
REG3 = _VAL2FLD(self.MCastMissAct >> ItemVLAN_REG2_MCastMissHi_Offs, ItemVLAN_REG3_MCastMissHi_Pos, ItemVLAN_REG3_MCastMissHi_Msk) \
| _VAL2FLD(self.MSTPAct, ItemVLAN_REG3_MSTP_Pos, ItemVLAN_REG3_MSTP_Msk) \
| _VAL2FLD(self.isValidREG1, ItemVLAN_REG3_IsValidREG1_Pos, ItemVLAN_REG3_IsValidREG1_Msk) \
| _VAL2FLD(self.isValidREG2, ItemVLAN_REG3_IsValidREG2_Pos, ItemVLAN_REG3_IsValidREG2_Msk) \
| _VAL2FLD(self.isValidREG3, ItemVLAN_REG3_IsValidREG3_Pos, ItemVLAN_REG3_IsValidREG3_Msk) \
| _VAL2FLD(self.isValidREG4, ItemVLAN_REG3_IsValidREG4_Pos, ItemVLAN_REG3_IsValidREG4_Msk) \
| _VAL2FLD(self.isValidREG5, ItemVLAN_REG3_IsValidREG5_Pos, ItemVLAN_REG3_IsValidREG5_Msk) \
| _VAL2FLD(self.port, ItemVLAN_REG3_PortNum_Pos, ItemVLAN_REG3_PortNum_Msk) \
| _VAL2FLD(self.collizPtr, ItemVLAN_REG3_CollizPtr_Pos, ItemVLAN_REG3_CollizPtr_Msk)
#REG4
REG4 = _VAL2FLD(self.isValidColiz, ItemVLAN_REG4_IsValidCollPtr_Pos, ItemVLAN_REG4_IsValidCollPtr_Msk) \
| _VAL2FLD(self.isActive, ItemVLAN_REG4_IsActive_Pos, ItemVLAN_REG4_IsActive_Msk)
#PACK to Buff
#print(hex(REG1), hex(REG2), hex(REG3), hex(REG4))
struct.pack_into("LLLL", buff, offs, REG1, REG2, REG3, REG4)
def pack(self, buff, offs):
REG1 = _VAL2FLD(self.TPID, STRUC1_PORT_TPID_Pos, STRUC1_PORT_TPID_Msk) \
| _VAL2FLD(self.Fallback, STRUC1_PORT_FALLBACK_BDID_Pos, STRUC1_PORT_FALLBACK_BDID_Msk)
REG2 = _VAL2FLD(self.shutDown, STRUC2_PORT_SHUTDOWN_Pos, STRUC2_PORT_SHUTDOWN_Msk) \
| _VAL2FLD(self.AFT, STRUC2_PORT_AFT_Pos, STRUC2_PORT_AFT_Msk, ) \
| _VAL2FLD(self.Blockstate, STRUC2_PORT_BLOCKSTATE_Pos, STRUC2_PORT_BLOCKSTATE_Msk) \
| _VAL2FLD(self.defCFI, STRUC2_PORT_DEF_CFI_Pos, STRUC2_PORT_DEF_CFI_Msk) \
| _VAL2FLD(self.defPRI, STRUC2_PORT_DEF_PRI_Pos, STRUC2_PORT_DEF_PRI_Msk) \
| _VAL2FLD(self.defTC, STRUC2_PORT_DEF_TC_Pos, STRUC2_PORT_DEF_TC_Msk) \
| _VAL2FLD(self.trusted, STRUC2_PORT_TRUSTED_Pos, STRUC2_PORT_TRUSTED_Msk) \
| _VAL2FLD(self.vidPreffix, STRUC2_PORT_VID_PREFIX_Pos, STRUC2_PORT_VID_PREFIX_Msk) \
| _VAL2FLD(self.UntagBTable,STRUC2_PORT_UNTAG_FROM_BTABLE_Pos, STRUC2_PORT_UNTAG_FROM_BTABLE_Msk)
#PACK to Buff
struct.pack_into("LL", buff, offs, REG1, REG2)
return offs + self.packLen
def pack(self, buff, offs):
mac64 = int(self.MAC.translate(self.MAC.maketrans('', '', ':.- ')), 16)
#print('mac64_TX: ', hex(mac64) )
REG1 = (mac64 >> 16) & 0xFFFFFFFF
REG2 = _VAL2FLD(mac64, ItemMAC_REG2_MAC_Lo16_Pos, ItemMAC_REG2_MAC_Lo16_Msk) \
| _VAL2FLD(self.vlanID, ItemMAC_REG2_VlanID_Pos, ItemMAC_REG2_VlanID_Msk) \
| _VAL2FLD(self.forwPorts, ItemMAC_REG2_PortListL_Pos, ItemMAC_REG2_PortListL_Msk)
REG3 = _VAL2FLD(self.forwPorts >> ItemMAC_REG3_ForwPortsHi_Offs, ItemMAC_REG3_PortListH_Pos, ItemMAC_REG3_PortListH_Msk) \
| _VAL2FLD(self.tc, ItemMAC_REG3_TC_Pos, ItemMAC_REG3_TC_Msk) \
| _VAL2FLD(self.action, ItemMAC_REG3_Actions_Pos, ItemMAC_REG3_Actions_Msk) \
| _VAL2FLD(self.cutThrough, ItemMAC_REG3_CutThrough_Pos, ItemMAC_REG3_CutThrough_Msk) \
| _VAL2FLD(self.isFresh, ItemMAC_REG3_IsFresh_Pos, ItemMAC_REG3_IsFresh_Msk) \
| _VAL2FLD(self.isStatic, ItemMAC_REG3_IsStatic_Pos, ItemMAC_REG3_IsStatic_Msk) \
| _VAL2FLD(self.isValidREG1, ItemMAC_REG3_IsValidREG1_Pos, ItemMAC_REG3_IsValidREG1_Msk) \
| _VAL2FLD(self.isValidREG2, ItemMAC_REG3_IsValidREG2_Pos, ItemMAC_REG3_IsValidREG2_Msk) \
| _VAL2FLD(self.isValidREG3, ItemMAC_REG3_IsValidREG3_Pos, ItemMAC_REG3_IsValidREG3_Msk) \
| _VAL2FLD(self.isValidREG4, ItemMAC_REG3_IsValidREG4_Pos, ItemMAC_REG3_IsValidREG4_Msk)
REG4 = _VAL2FLD(self.isValidREG5, ItemMAC_REG4_IsValidREG5_Pos, ItemMAC_REG4_IsValidREG5_Msk) \
| _VAL2FLD(self.port, ItemMAC_REG4_PortNum_Pos, ItemMAC_REG4_PortNum_Msk) \
| _VAL2FLD(self.collizPtr, ItemMAC_REG4_CollizPtr_Pos, ItemMAC_REG4_CollizPtr_Msk) \
| _VAL2FLD(self.isValidColiz, ItemMAC_REG4_IsValidCollPtr_Pos, ItemMAC_REG4_IsValidCollPtr_Msk) \
| _VAL2FLD(self.isActive, ItemMAC_REG4_IsActive_Pos, ItemMAC_REG4_IsActive_Msk)
struct.pack_into("LLLL", buff, offs, REG1, REG2, REG3, REG4)