def test_8b_cast(self, t=int8_t):
w = t.bit_length()
if t.signed:
ut = Bits3t(w)
else:
ut = t
t = Bits3t(w, True)
self.assertEqual(int(t.from_py(-1).cast(ut)), mask(w))
self.assertEqual(int(t.from_py(-1).cast_sign(False)), mask(w))
self.assertEqual(int(t.from_py(-1).cast_sign(None)), mask(w))
self.assertEqual(int(t.from_py(1).cast(ut)), 1)
self.assertEqual(int(t.from_py(0).cast(ut)), 0)
self.assertEqual(int(ut.from_py(1).cast(t)), 1)
self.assertEqual(int(ut.from_py(mask(w)).cast(t)), -1)
self.assertEqual(int(ut.from_py(mask(w)).cast_sign(True)), -1)
def __init__(self, bit_length, signed=BITS_DEFAUTL_SIGNED,
force_vector=BITS_DEFAUTL_FORCEVECTOR,
negated=BITS_DEFAUTL_NEGATED,
name=None,
const=False,
strict_sign=True, strict_width=True):
"""
:param negated: if true the value is in negated form
"""
self.negated = negated
HdlType.__init__(self, const=const)
bit_length = int(bit_length)
assert bit_length > 0, bit_length
Bits3t.__init__(self, bit_length, signed, name=name,
force_vector=force_vector,
strict_sign=strict_sign, strict_width=strict_width)
def test_4b_sign_cast(self):
t = Bits3t(4)
v = t.from_py(0xf)
self.assertEqual(int(v), 0xf)
self.assertEqual(int(v.cast_sign(True)), -1)
self.assertEqual(int(v.cast_sign(True).cast_sign(False)), 0xf)
v = t.from_py(0xe)
self.assertEqual(int(v), 0xe)
self.assertEqual(int(v.cast_sign(True)), -2)
self.assertEqual(int(v.cast_sign(True).cast_sign(False)), 0xe)
def test_8b_xor(self, t=int8_t):
ut = Bits3t(t.bit_length())
m = t.all_mask()
if t.signed:
v = t.from_py(-1)
else:
v = t.from_py(m)
ae = self.assertEqual
ae(v ^ ut.from_py(m), 0)
if t.signed:
ae(v ^ ut.from_py(0), -1)
ae(v ^ ut.from_py(1), -2)
else:
ae(v ^ ut.from_py(0), m)
ae(v ^ ut.from_py(1), m ^ 1)
def test_8b_or(self, t=int8_t):
ut = Bits3t(t.bit_length())
m = t.all_mask()
low, up, intLow, intUp = self.getMinMaxVal(t)
ae = self.assertEqual
if t.signed:
v = t.from_py(-1)
else:
v = t.from_py(m)
if t.signed:
ae(v | ut.from_py(m), -1)
ae(v | ut.from_py(0), -1)
ae(low | ut.from_py(m), -1)
ae(up | ut.from_py(m), -1)
ae(low | ut.from_py(0), intLow)
ae(up | ut.from_py(0), intUp)
def test_8b_le(self, t=int8_t):
ut = Bits3t(t.bit_length())
low, up, _, _ = self.getMinMaxVal(t)
if t.signed:
self.assertTrue(t.from_py(-1) <= -1)
self.assertTrue(t.from_py(0) <= 0)
self.assertTrue(t.from_py(1) <= 1)
self.assertTrue(up <= up)
self.assertTrue(low <= low)
if t.signed:
self.assertFalse(t.from_py(0) <= -1)
self.assertTrue(t.from_py(-1) <= 0)
self.assertFalse(up <= low)
self.assertTrue(low <= up)
if t.signed:
with self.assertRaises(TypeError):
t.from_py(0) <= ut.from_py(0)
def test_8b_mul(self, t=int8_t):
w = t.bit_length()
low, up, _, _ = self.getMinMaxVal(t)
ut = Bits3t(w)
ae = self.assertEqual
if t.signed:
ae(int(t.from_py(-1) * t.from_py(-1)), 1)
ae(int(t.from_py(1) * t.from_py(1)), 1)
if t.signed:
ae(int(t.from_py(0) * t.from_py(-1)), 0)
ae(int(ut.from_py(0) * ut.from_py(1)), 0)
ae(int(ut.from_py(mask(w)) * ut.from_py(2)), (mask(w) << 1) & mask(w))
if t.signed:
ae(int(t.from_py(-1) * ut.from_py(2)), -2)
ae(low * t.from_py(2), 0)
if t.signed:
ae(up * t.from_py(2), -2)
m = up * t.from_py(None)
ae(valToInt(m), None)
def test_8b_gt(self, t=int8_t):
ut = Bits3t(t.bit_length())
low, up, _, _ = self.getMinMaxVal(t)
if t.signed:
self.assertFalse(t.from_py(-1) > -1)
self.assertFalse(t.from_py(0) > 0)
self.assertFalse(t.from_py(1) > 1)
self.assertFalse(up > up)
self.assertFalse(low > low)
if t.signed:
self.assertTrue(t.from_py(0) > -1)
self.assertFalse(t.from_py(-1) > 0)
self.assertTrue(up > low)
self.assertFalse(low > up)
if t.signed:
with self.assertRaises(TypeError):
t.from_py(0) > ut.from_py(0)
def test_8b_and(self, t=int8_t):
low, up, intLow, intUp = self.getMinMaxVal(t)
ut = Bits3t(t.bit_length())
m = t.all_mask()
ae = self.assertEqual
if t.signed:
v = t.from_py(-1)
else:
v = t.from_py(m)
if t.signed:
ae(v & ut.from_py(m), -1)
ae(v & ut.from_py(0), 0)
ae(v & ut.from_py(1), 1)
ae(low & up, 0)
if t.signed:
ae(low & -1, intLow)
else:
ae(low & m, intLow)
ae(up & ut.from_py(m), intUp)
def test_BitsIndexTypes(self):
t = Bits3t(8)
v = t.from_py(1)
with self.assertRaises(TypeError):
v[object()]
with self.assertRaises(IndexError):
v[9:]
with self.assertRaises(IndexError):
v[:-1]
p = 2
self.assertEqual(v[p]._dtype.bit_length(), 1)
p2 = slice(p, 0)
self.assertEqual(v[p2]._dtype.bit_length(), 2)
v[p] = 1
self.assertTrue(v._eq(5))
v[p2] = 2
self.assertTrue(v._eq(6))
with self.assertRaises(TypeError):
v[None] = 2
v[:] = 0
self.assertTrue(v._eq(0))
v[2] = 1
self.assertTrue(v._eq(4))
v[3:] = p
self.assertTrue(v._eq(2))
v[1] = None
with self.assertRaises(ValueError):
int(v)
with self.assertRaises(TypeError):
v["asfs"]
def test_8b_eq(self, t=int8_t):
ut = Bits3t(t.bit_length())
low, up, _, _ = self.getMinMaxVal(t)
if t.signed:
self.assertTrue(t.from_py(-1)._eq(-1))
self.assertTrue(t.from_py(0)._eq(0))
self.assertTrue(up == up)
self.assertTrue(low == low)
if t.signed:
self.assertFalse(t.from_py(0)._eq(-1))
self.assertFalse(t.from_py(-1)._eq(0))
self.assertFalse(t.from_py(0) == 1)
self.assertFalse(t.from_py(1) == 0)
self.assertFalse(up == low)
self.assertFalse(low == up)
if t.signed:
with self.assertRaises(TypeError):
t.from_py(0)._eq(ut.from_py(0))
class Ram_dp(BasicRtlSimModel):
arr_t_0 = Bits3t(64, 0)[256]
def __init__(self, sim: "BasicRtlSimulator", name="Ram_dp"):
BasicRtlSimModel.__init__(self, sim, name=name)
# ports
self.io.a_addr = BasicRtlSimProxy(sim, self, "a_addr", Bits3t(8, 0),
None)
self.io.a_clk = BasicRtlSimProxy(sim, self, "a_clk", Bits3t(1, 0),
None)
self.io.a_din = BasicRtlSimProxy(sim, self, "a_din", Bits3t(64, 0),
None)
self.io.a_dout = BasicRtlSimProxy(sim, self, "a_dout", Bits3t(64, 0),
None)
self.io.a_en = BasicRtlSimProxy(sim, self, "a_en", Bits3t(1, 0), None)
self.io.a_we = BasicRtlSimProxy(sim, self, "a_we", Bits3t(1, 0), None)
self.io.b_addr = BasicRtlSimProxy(sim, self, "b_addr", Bits3t(8, 0),
None)
self.io.b_clk = BasicRtlSimProxy(sim, self, "b_clk", Bits3t(1, 0),
None)
self.io.b_din = BasicRtlSimProxy(sim, self, "b_din", Bits3t(64, 0),
None)
self.io.b_dout = BasicRtlSimProxy(sim, self, "b_dout", Bits3t(64, 0),
None)
self.io.b_en = BasicRtlSimProxy(sim, self, "b_en", Bits3t(1, 0), None)
self.io.b_we = BasicRtlSimProxy(sim, self, "b_we", Bits3t(1, 0), None)
# internal signals
self.io.ram_memory = BasicRtlSimProxy(sim, self, "ram_memory",
self.arr_t_0, None)
self.const_0 = Array3val(self.arr_t_0, {}, 0)
self.const_0_0 = Bits3val(Bits3t(64, 0), 0, 0)
self.const_1_0 = Bits3val(Bits3t(1, 0), 1, 1)
# component instances
def _init_body(self):
self._interfaces = (
self.io.a_addr,
self.io.a_clk,
self.io.a_din,
self.io.a_dout,
self.io.a_en,
self.io.a_we,
self.io.b_addr,
self.io.b_clk,
self.io.b_din,
self.io.b_dout,
self.io.b_en,
self.io.b_we,
self.io.ram_memory,
)
self._processes = (
self.assig_process_a_dout,
self.assig_process_b_dout,
)
self._units = ()
sensitivity(self.assig_process_a_dout, ((True, False), self.io.a_clk))
self._outputs[self.assig_process_a_dout] = (
self.io.a_dout,
self.io.ram_memory,
)
sensitivity(self.assig_process_b_dout, ((True, False), self.io.b_clk))
self._outputs[self.assig_process_b_dout] = (
self.io.b_dout,
self.io.ram_memory,
)
for u in self._units:
u._init_body()
# sensitivity: HdlOpType.RISING a_clk
def assig_process_a_dout(self):
(
c,
cVld,
) = sim_eval_cond(self.io.a_clk._onRisingEdge()
& self.io.a_en.val._eq(self.const_1_0))
if not cVld:
self.io.ram_memory.val_next = (
self.const_0,
1,
)
self.io.a_dout.val_next = (
self.const_0_0,
1,
)
elif c:
(
c,
cVld,
) = sim_eval_cond(self.io.a_we.val._eq(self.const_1_0))
if not cVld:
self.io.ram_memory.val_next = (
self.const_0,
1,
)
elif c:
self.io.ram_memory.val_next = (
self.io.a_din.val,
(self.io.a_addr.val, ),
1,
)
else:
pass
self.io.a_dout.val_next = (
self.io.ram_memory.val[self.io.a_addr.val],
1,
)
else:
pass
# sensitivity: HdlOpType.RISING b_clk
def assig_process_b_dout(self):
(
c,
cVld,
) = sim_eval_cond(self.io.b_clk._onRisingEdge()
& self.io.b_en.val._eq(self.const_1_0))
if not cVld:
self.io.ram_memory.val_next = (
self.const_0,
1,
)
self.io.b_dout.val_next = (
self.const_0_0,
1,
)
elif c:
(
c,
cVld,
) = sim_eval_cond(self.io.b_we.val._eq(self.const_1_0))
if not cVld:
self.io.ram_memory.val_next = (
self.const_0,
1,
)
elif c:
self.io.ram_memory.val_next = (
self.io.b_din.val,
(self.io.b_addr.val, ),
1,
)
else:
pass
self.io.b_dout.val_next = (
self.io.ram_memory.val[self.io.b_addr.val],
1,
)
else:
pass
def test_BitsMulInvalidType(self):
t = Bits3t(8)
v = t.from_py(1)
with self.assertRaises(TypeError):
v * "a"
def vec(val, w):
t = Bits3t(w)
return t.from_py(val)
def __init__(self, sim: "BasicRtlSimulator", name="GroupOfBlockrams"):
BasicRtlSimModel.__init__(self, sim, name=name)
# ports
self.io.addr = BasicRtlSimProxy(sim, self, "addr", Bits3t(8, 0), None)
self.io.clk = BasicRtlSimProxy(sim, self, "clk", Bits3t(1, 0), None)
self.io.en = BasicRtlSimProxy(sim, self, "en", Bits3t(1, 0), None)
self.io.in_r_a = BasicRtlSimProxy(sim, self, "in_r_a", Bits3t(64, 0),
None)
self.io.in_r_b = BasicRtlSimProxy(sim, self, "in_r_b", Bits3t(64, 0),
None)
self.io.in_w_a = BasicRtlSimProxy(sim, self, "in_w_a", Bits3t(64, 0),
None)
self.io.in_w_b = BasicRtlSimProxy(sim, self, "in_w_b", Bits3t(64, 0),
None)
self.io.out_r_a = BasicRtlSimProxy(sim, self, "out_r_a", Bits3t(64, 0),
None)
self.io.out_r_b = BasicRtlSimProxy(sim, self, "out_r_b", Bits3t(64, 0),
None)
self.io.out_w_a = BasicRtlSimProxy(sim, self, "out_w_a", Bits3t(64, 0),
None)
self.io.out_w_b = BasicRtlSimProxy(sim, self, "out_w_b", Bits3t(64, 0),
None)
self.io.we = BasicRtlSimProxy(sim, self, "we", Bits3t(1, 0), None)
# internal signals
self.io.sig_bramR_a_addr = BasicRtlSimProxy(sim, self,
"sig_bramR_a_addr",
Bits3t(8, 0), None)
self.io.sig_bramR_a_clk = BasicRtlSimProxy(sim, self,
"sig_bramR_a_clk",
Bits3t(1, 0), None)
self.io.sig_bramR_a_din = BasicRtlSimProxy(sim, self,
"sig_bramR_a_din",
Bits3t(64, 0), None)
self.io.sig_bramR_a_dout = BasicRtlSimProxy(sim, self,
"sig_bramR_a_dout",
Bits3t(64, 0), None)
self.io.sig_bramR_a_en = BasicRtlSimProxy(sim, self, "sig_bramR_a_en",
Bits3t(1, 0), None)
self.io.sig_bramR_a_we = BasicRtlSimProxy(sim, self, "sig_bramR_a_we",
Bits3t(1, 0), None)
self.io.sig_bramR_b_addr = BasicRtlSimProxy(sim, self,
"sig_bramR_b_addr",
Bits3t(8, 0), None)
self.io.sig_bramR_b_clk = BasicRtlSimProxy(sim, self,
"sig_bramR_b_clk",
Bits3t(1, 0), None)
self.io.sig_bramR_b_din = BasicRtlSimProxy(sim, self,
"sig_bramR_b_din",
Bits3t(64, 0), None)
self.io.sig_bramR_b_dout = BasicRtlSimProxy(sim, self,
"sig_bramR_b_dout",
Bits3t(64, 0), None)
self.io.sig_bramR_b_en = BasicRtlSimProxy(sim, self, "sig_bramR_b_en",
Bits3t(1, 0), None)
self.io.sig_bramR_b_we = BasicRtlSimProxy(sim, self, "sig_bramR_b_we",
Bits3t(1, 0), None)
self.io.sig_bramW_a_addr = BasicRtlSimProxy(sim, self,
"sig_bramW_a_addr",
Bits3t(8, 0), None)
self.io.sig_bramW_a_clk = BasicRtlSimProxy(sim, self,
"sig_bramW_a_clk",
Bits3t(1, 0), None)
self.io.sig_bramW_a_din = BasicRtlSimProxy(sim, self,
"sig_bramW_a_din",
Bits3t(64, 0), None)
self.io.sig_bramW_a_dout = BasicRtlSimProxy(sim, self,
"sig_bramW_a_dout",
Bits3t(64, 0), None)
self.io.sig_bramW_a_en = BasicRtlSimProxy(sim, self, "sig_bramW_a_en",
Bits3t(1, 0), None)
self.io.sig_bramW_a_we = BasicRtlSimProxy(sim, self, "sig_bramW_a_we",
Bits3t(1, 0), None)
self.io.sig_bramW_b_addr = BasicRtlSimProxy(sim, self,
"sig_bramW_b_addr",
Bits3t(8, 0), None)
self.io.sig_bramW_b_clk = BasicRtlSimProxy(sim, self,
"sig_bramW_b_clk",
Bits3t(1, 0), None)
self.io.sig_bramW_b_din = BasicRtlSimProxy(sim, self,
"sig_bramW_b_din",
Bits3t(64, 0), None)
self.io.sig_bramW_b_dout = BasicRtlSimProxy(sim, self,
"sig_bramW_b_dout",
Bits3t(64, 0), None)
self.io.sig_bramW_b_en = BasicRtlSimProxy(sim, self, "sig_bramW_b_en",
Bits3t(1, 0), None)
self.io.sig_bramW_b_we = BasicRtlSimProxy(sim, self, "sig_bramW_b_we",
Bits3t(1, 0), None)
# component instances
self.bramR_inst = Ram_dp(sim, "bramR_inst")
self.bramW_inst = Ram_dp(sim, "bramW_inst")
#!/usr/bin/env python3
# -*- coding: UTF-8 -*-
from pyMathBitPrecise.bits3t import Bits3t
import unittest
int8_t = Bits3t(8, signed=True)
uint8_t = Bits3t(8, signed=False)
int512_t = Bits3t(512, signed=True)
uint512_t = Bits3t(512, signed=False)
def valToInt(val):
if val._is_full_valid():
return int(val)
else:
return None
class Bits3tBaseTC(unittest.TestCase):
def getMinMaxVal(self, t):
m = t.all_mask()
if t.signed:
intLow = -(m // 2) - 1
intUp = m // 2
else:
intLow = 0
intUp = m
return t.from_py(intLow), t.from_py(intUp), intLow, intUp
def assertEqual(self, first, second, msg=None):
def test_8b_16b_concat(self):
t0 = uint8_t
t1 = Bits3t(16)
self.assertEqual(int(t0.from_py(0xff)._concat(
t1.from_py(1))), (0xff << 16) | 1)
def __eq__(self, other):
return Bits3t.__eq__(self, other) and self.const == other.const
def __hash__(self):
return hash((Bits3t.__hash__(self), self.const))
class Showcase0(BasicRtlSimModel):
arr_t_0 = Bits3t(8, 1)[4]
arr_t_1 = Bits3t(8, 0)[4]
def __init__(self, sim: "BasicRtlSimulator", name="Showcase0"):
BasicRtlSimModel.__init__(self, sim, name=name)
# ports
self.io.a = BasicRtlSimProxy(sim, self, "a", Bits3t(32, 0), None)
self.io.b = BasicRtlSimProxy(sim, self, "b", Bits3t(32, 1), None)
self.io.c = BasicRtlSimProxy(sim, self, "c", Bits3t(32, 0), None)
self.io.clk = BasicRtlSimProxy(sim, self, "clk", Bits3t(1, 0), None)
self.io.cmp_0 = BasicRtlSimProxy(sim, self, "cmp_0", Bits3t(1, 0),
None)
self.io.cmp_1 = BasicRtlSimProxy(sim, self, "cmp_1", Bits3t(1, 0),
None)
self.io.cmp_2 = BasicRtlSimProxy(sim, self, "cmp_2", Bits3t(1, 0),
None)
self.io.cmp_3 = BasicRtlSimProxy(sim, self, "cmp_3", Bits3t(1, 0),
None)
self.io.cmp_4 = BasicRtlSimProxy(sim, self, "cmp_4", Bits3t(1, 0),
None)
self.io.cmp_5 = BasicRtlSimProxy(sim, self, "cmp_5", Bits3t(1, 0),
None)
self.io.contOut = BasicRtlSimProxy(sim, self, "contOut", Bits3t(32, 0),
None)
self.io.d = BasicRtlSimProxy(sim, self, "d", Bits3t(32, 0), None)
self.io.e = BasicRtlSimProxy(sim, self, "e", Bits3t(1, 0), None)
self.io.f = BasicRtlSimProxy(sim, self, "f", Bits3t(1, 0), None)
self.io.fitted = BasicRtlSimProxy(sim, self, "fitted", Bits3t(16, 0),
None)
self.io.g = BasicRtlSimProxy(sim, self, "g", Bits3t(8, 0), None)
self.io.h = BasicRtlSimProxy(sim, self, "h", Bits3t(8, 0), None)
self.io.i = BasicRtlSimProxy(sim, self, "i", Bits3t(2, 0), None)
self.io.j = BasicRtlSimProxy(sim, self, "j", Bits3t(8, 0), None)
self.io.k = BasicRtlSimProxy(sim, self, "k", Bits3t(32, 0), None)
self.io.out = BasicRtlSimProxy(sim, self, "out", Bits3t(1, 0), None)
self.io.output = BasicRtlSimProxy(sim, self, "output", Bits3t(1, 0),
None)
self.io.rst_n = BasicRtlSimProxy(sim, self, "rst_n", Bits3t(1, 0),
None)
self.io.sc_signal = BasicRtlSimProxy(sim, self, "sc_signal",
Bits3t(8, 0), None)
# internal signals
self.const_private_signal = Bits3val(Bits3t(32, 0), 123, 4294967295)
self.io.fallingEdgeRam = BasicRtlSimProxy(sim, self, "fallingEdgeRam",
self.arr_t_0, None)
self.io.r = BasicRtlSimProxy(sim, self, "r", Bits3t(1, 0),
Bits3val(Bits3t(1, 0), 0, 1))
self.io.r_0 = BasicRtlSimProxy(sim, self, "r_0", Bits3t(2, 0),
Bits3val(Bits3t(2, 0), 0, 3))
self.io.r_1 = BasicRtlSimProxy(sim, self, "r_1", Bits3t(2, 0),
Bits3val(Bits3t(2, 0), 0, 3))
self.io.r_next = BasicRtlSimProxy(sim, self, "r_next", Bits3t(1, 0),
None)
self.io.r_next_0 = BasicRtlSimProxy(sim, self, "r_next_0",
Bits3t(2, 0), None)
self.io.r_next_1 = BasicRtlSimProxy(sim, self, "r_next_1",
Bits3t(2, 0), None)
self.rom = Array3val(
self.arr_t_1, {
0: Bits3val(Bits3t(8, 0), 0, 255),
1: Bits3val(Bits3t(8, 0), 1, 255),
2: Bits3val(Bits3t(8, 0), 2, 255),
3: Bits3val(Bits3t(8, 0), 3, 255)
}, 1)
self.const_4_0 = Bits3val(Bits3t(32, 0), 4, 4294967295)
self.const_4_1 = Bits3val(Bits3t(32, 1), 4, 4294967295)
self.const_0 = Array3val(self.arr_t_0, {}, 0)
self.const_0_0 = Bits3val(Bits3t(32, 0), 0, 0)
self.const_1 = slice(8, 0, -1)
self.const_0_1 = Bits3val(Bits3t(24, 0), 0, 16777215)
self.const_2 = slice(16, 0, -1)
self.const_1_0 = Bits3val(Bits3t(32, 1), 1, 4294967295)
self.const_0_2 = Bits3val(Bits3t(32, 1), 0, 4294967295)
self.const_3 = slice(6, 0, -1)
self.const_0_3 = Bits3val(Bits3t(8, 0), 0, 0)
self.const_2_0 = Bits3val(Bits3t(32, 1), 2, 4294967295)
self.const_1_1 = Bits3val(Bits3t(1, 0), 1, 1)
self.const_0_4 = Bits3val(Bits3t(8, 0), 0, 255)
self.const_1_2 = Bits3val(Bits3t(8, 0), 1, 255)
self.const_2_1 = Bits3val(Bits3t(8, 0), 2, 255)
self.const_0_5 = Bits3val(Bits3t(1, 0), 0, 1)
self.const_0_6 = Bits3val(Bits3t(1, 0), 0, 0)
self.const_0_7 = Bits3val(Bits3t(2, 0), 0, 0)
self.const_0_8 = Bits3val(Bits3t(2, 0), 0, 3)
self.const_1_3 = Bits3val(Bits3t(32, 0), 1, 4294967295)
self.const_2_2 = Bits3val(Bits3t(32, 0), 2, 4294967295)
self.const_3_0 = Bits3val(Bits3t(32, 0), 3, 4294967295)
self.const_3_1 = Bits3val(Bits3t(8, 0), 3, 255)
self.const_4_2 = Bits3val(Bits3t(8, 0), 4, 255)
# component instances
def _init_body(self):
self._interfaces = (
self.io.a,
self.io.b,
self.io.c,
self.io.clk,
self.io.cmp_0,
self.io.cmp_1,
self.io.cmp_2,
self.io.cmp_3,
self.io.cmp_4,
self.io.cmp_5,
self.io.contOut,
self.io.d,
self.io.e,
self.io.f,
self.io.fitted,
self.io.g,
self.io.h,
self.io.i,
self.io.j,
self.io.k,
self.io.out,
self.io.output,
self.io.rst_n,
self.io.sc_signal,
self.io.fallingEdgeRam,
self.io.r,
self.io.r_0,
self.io.r_1,
self.io.r_next,
self.io.r_next_0,
self.io.r_next_1,
)
self._processes = (
self.assig_process_c,
self.assig_process_cmp_0,
self.assig_process_cmp_1,
self.assig_process_cmp_2,
self.assig_process_cmp_3,
self.assig_process_cmp_4,
self.assig_process_cmp_5,
self.assig_process_contOut,
self.assig_process_f,
self.assig_process_fallingEdgeRam,
self.assig_process_fitted,
self.assig_process_g,
self.assig_process_h,
self.assig_process_j,
self.assig_process_out,
self.assig_process_output,
self.assig_process_r,
self.assig_process_r_next,
self.assig_process_r_next_0,
self.assig_process_r_next_1,
self.assig_process_sc_signal,
)
self._units = ()
sensitivity(self.assig_process_c, self.io.a, self.io.b)
self._outputs[self.assig_process_c] = (self.io.c, )
sensitivity(self.assig_process_cmp_0, self.io.a)
self._outputs[self.assig_process_cmp_0] = (self.io.cmp_0, )
sensitivity(self.assig_process_cmp_1, self.io.a)
self._outputs[self.assig_process_cmp_1] = (self.io.cmp_1, )
sensitivity(self.assig_process_cmp_2, self.io.b)
self._outputs[self.assig_process_cmp_2] = (self.io.cmp_2, )
sensitivity(self.assig_process_cmp_3, self.io.b)
self._outputs[self.assig_process_cmp_3] = (self.io.cmp_3, )
sensitivity(self.assig_process_cmp_4, self.io.b)
self._outputs[self.assig_process_cmp_4] = (self.io.cmp_4, )
sensitivity(self.assig_process_cmp_5, self.io.b)
self._outputs[self.assig_process_cmp_5] = (self.io.cmp_5, )
sensitivity(self.assig_process_contOut, )
self._outputs[self.assig_process_contOut] = (self.io.contOut, )
sensitivity(self.assig_process_f, self.io.r)
self._outputs[self.assig_process_f] = (self.io.f, )
sensitivity(self.assig_process_fallingEdgeRam,
((False, True), self.io.clk))
self._outputs[self.assig_process_fallingEdgeRam] = (
self.io.fallingEdgeRam,
self.io.k,
)
sensitivity(self.assig_process_fitted, self.io.a)
self._outputs[self.assig_process_fitted] = (self.io.fitted, )
sensitivity(self.assig_process_g, self.io.a, self.io.b)
self._outputs[self.assig_process_g] = (self.io.g, )
sensitivity(self.assig_process_h, self.io.a, self.io.r)
self._outputs[self.assig_process_h] = (self.io.h, )
sensitivity(self.assig_process_j, ((True, False), self.io.clk))
self._outputs[self.assig_process_j] = (self.io.j, )
sensitivity(self.assig_process_out, )
self._outputs[self.assig_process_out] = (self.io.out, )
sensitivity(self.assig_process_output, )
self._outputs[self.assig_process_output] = (self.io.output, )
sensitivity(self.assig_process_r, ((True, False), self.io.clk))
self._outputs[self.assig_process_r] = (
self.io.r,
self.io.r_0,
self.io.r_1,
)
sensitivity(self.assig_process_r_next, self.io.i)
self._outputs[self.assig_process_r_next] = (self.io.r_next_0, )
sensitivity(self.assig_process_r_next_0, self.io.r_0)
self._outputs[self.assig_process_r_next_0] = (self.io.r_next_1, )
sensitivity(self.assig_process_r_next_1, self.io.e, self.io.r)
self._outputs[self.assig_process_r_next_1] = (self.io.r_next, )
sensitivity(self.assig_process_sc_signal, self.io.a)
self._outputs[self.assig_process_sc_signal] = (self.io.sc_signal, )
for u in self._units:
u._init_body()
# sensitivity: a, b
def assig_process_c(self):
self.io.c.val_next = (
self.io.a.val + self.io.b.val.cast_sign(True),
0,
)
# sensitivity: a
def assig_process_cmp_0(self):
self.io.cmp_0.val_next = (
self.io.a.val < self.const_4_0,
0,
)
# sensitivity: a
def assig_process_cmp_1(self):
self.io.cmp_1.val_next = (
self.io.a.val > self.const_4_0,
0,
)
# sensitivity: b
def assig_process_cmp_2(self):
self.io.cmp_2.val_next = (
self.io.b.val <= self.const_4_1,
0,
)
# sensitivity: b
def assig_process_cmp_3(self):
self.io.cmp_3.val_next = (
self.io.b.val >= self.const_4_1,
0,
)
# sensitivity: b
def assig_process_cmp_4(self):
self.io.cmp_4.val_next = (
self.io.b.val != self.const_4_1,
0,
)
# sensitivity: b
def assig_process_cmp_5(self):
self.io.cmp_5.val_next = (
self.io.b.val._eq(self.const_4_1),
0,
)
# sensitivity:
def assig_process_contOut(self):
self.io.contOut.val_next = (
self.const_private_signal,
0,
)
# sensitivity: r
def assig_process_f(self):
self.io.f.val_next = (
self.io.r.val,
0,
)
# sensitivity: HdlOpType.FALLING clk
def assig_process_fallingEdgeRam(self):
(
c,
cVld,
) = sim_eval_cond(self.io.clk._onFallingEdge())
if not cVld:
self.io.fallingEdgeRam.val_next = (
self.const_0,
1,
)
self.io.k.val_next = (
self.const_0_0,
1,
)
elif c:
self.io.fallingEdgeRam.val_next = (
self.io.a.val[self.const_1].cast_sign(False),
(self.io.r_1.val, ),
1,
)
self.io.k.val_next = (
self.const_0_1._concat(self.io.fallingEdgeRam.val[
self.io.r_1.val].cast_sign(True)),
1,
)
else:
pass
# sensitivity: a
def assig_process_fitted(self):
self.io.fitted.val_next = (
self.io.a.val[self.const_2],
0,
)
# sensitivity: a, b
def assig_process_g(self):
self.io.g.val_next = (
(self.io.a.val[self.const_1_0]
& self.io.b.val[self.const_1_0])._concat(
self.io.a.val[self.const_0_2] ^ self.io.b.val[self.const_0_2]
| self.io.a.val[self.const_1_0])._concat(
self.io.a.val[self.const_3]),
0,
)
# sensitivity: a, r
def assig_process_h(self):
(
c,
cVld,
) = sim_eval_cond(self.io.a.val[self.const_2_0]._eq(self.const_1_1))
if not cVld:
self.io.h.val_next = (
self.const_0_3,
0,
)
elif c:
(
c,
cVld,
) = sim_eval_cond(self.io.r.val._eq(self.const_1_1))
if not cVld:
self.io.h.val_next = (
self.const_0_3,
0,
)
elif c:
self.io.h.val_next = (
self.const_0_4,
0,
)
else:
(
c,
cVld,
) = sim_eval_cond(self.io.a.val[self.const_1_0]._eq(
self.const_1_1))
if not cVld:
self.io.h.val_next = (
self.const_0_3,
0,
)
elif c:
self.io.h.val_next = (
self.const_1_2,
0,
)
else:
self.io.h.val_next = (
self.const_2_1,
0,
)
else:
pass
# sensitivity: HdlOpType.RISING clk
def assig_process_j(self):
(
c,
cVld,
) = sim_eval_cond(self.io.clk._onRisingEdge())
if not cVld:
self.io.j.val_next = (
self.const_0_3,
1,
)
elif c:
self.io.j.val_next = (
self.rom[self.io.r_1.val],
1,
)
else:
pass
# sensitivity:
def assig_process_out(self):
self.io.out.val_next = (
self.const_0_5,
0,
)
# sensitivity:
def assig_process_output(self):
self.io.output.val_next = (
self.const_0_6,
0,
)
# sensitivity: HdlOpType.RISING clk
def assig_process_r(self):
(
c,
cVld,
) = sim_eval_cond(self.io.clk._onRisingEdge())
if not cVld:
self.io.r_1.val_next = (
self.const_0_7,
1,
)
self.io.r_0.val_next = (
self.const_0_7,
1,
)
self.io.r.val_next = (
self.const_0_6,
1,
)
elif c:
(
c,
cVld,
) = sim_eval_cond(self.io.rst_n.val._eq(self.const_0_5))
if not cVld:
self.io.r_1.val_next = (
self.const_0_7,
1,
)
self.io.r_0.val_next = (
self.const_0_7,
1,
)
self.io.r.val_next = (
self.const_0_6,
1,
)
elif c:
self.io.r_1.val_next = (
self.const_0_8,
1,
)
self.io.r_0.val_next = (
self.const_0_8,
1,
)
self.io.r.val_next = (
self.const_0_5,
1,
)
else:
self.io.r_1.val_next = (
self.io.r_next_1.val,
1,
)
self.io.r_0.val_next = (
self.io.r_next_0.val,
1,
)
self.io.r.val_next = (
self.io.r_next.val,
1,
)
else:
pass
# sensitivity: i
def assig_process_r_next(self):
self.io.r_next_0.val_next = (
self.io.i.val,
0,
)
# sensitivity: r_0
def assig_process_r_next_0(self):
self.io.r_next_1.val_next = (
self.io.r_0.val,
0,
)
# sensitivity: e, r
def assig_process_r_next_1(self):
(
c,
cVld,
) = sim_eval_cond((~(self.io.r.val))._eq(self.const_1_1))
if not cVld:
self.io.r_next.val_next = (
self.const_0_6,
0,
)
elif c:
self.io.r_next.val_next = (
self.io.e.val,
0,
)
else:
self.io.r_next.val_next = (
self.io.r.val,
0,
)
# sensitivity: a
def assig_process_sc_signal(self):
(
c,
cVld,
) = sim_eval_cond(self.io.a.val._eq(self.const_1_3))
if not cVld:
self.io.sc_signal.val_next = (
self.const_0_3,
0,
)
elif c:
self.io.sc_signal.val_next = (
self.const_0_4,
0,
)
else:
(
c,
cVld,
) = sim_eval_cond(self.io.a.val._eq(self.const_2_2))
if not cVld:
self.io.sc_signal.val_next = (
self.const_0_3,
0,
)
elif c:
self.io.sc_signal.val_next = (
self.const_1_2,
0,
)
else:
(
c,
cVld,
) = sim_eval_cond(self.io.a.val._eq(self.const_3_0))
if not cVld:
self.io.sc_signal.val_next = (
self.const_0_3,
0,
)
elif c:
self.io.sc_signal.val_next = (
self.const_3_1,
0,
)
else:
self.io.sc_signal.val_next = (
self.const_4_2,
0,
)
def __init__(self, sim: "BasicRtlSimulator", name="Ram_dp"):
BasicRtlSimModel.__init__(self, sim, name=name)
# ports
self.io.a_addr = BasicRtlSimProxy(sim, self, "a_addr", Bits3t(8, 0),
None)
self.io.a_clk = BasicRtlSimProxy(sim, self, "a_clk", Bits3t(1, 0),
None)
self.io.a_din = BasicRtlSimProxy(sim, self, "a_din", Bits3t(64, 0),
None)
self.io.a_dout = BasicRtlSimProxy(sim, self, "a_dout", Bits3t(64, 0),
None)
self.io.a_en = BasicRtlSimProxy(sim, self, "a_en", Bits3t(1, 0), None)
self.io.a_we = BasicRtlSimProxy(sim, self, "a_we", Bits3t(1, 0), None)
self.io.b_addr = BasicRtlSimProxy(sim, self, "b_addr", Bits3t(8, 0),
None)
self.io.b_clk = BasicRtlSimProxy(sim, self, "b_clk", Bits3t(1, 0),
None)
self.io.b_din = BasicRtlSimProxy(sim, self, "b_din", Bits3t(64, 0),
None)
self.io.b_dout = BasicRtlSimProxy(sim, self, "b_dout", Bits3t(64, 0),
None)
self.io.b_en = BasicRtlSimProxy(sim, self, "b_en", Bits3t(1, 0), None)
self.io.b_we = BasicRtlSimProxy(sim, self, "b_we", Bits3t(1, 0), None)
# internal signals
self.io.ram_memory = BasicRtlSimProxy(sim, self, "ram_memory",
self.arr_t_0, None)
self.const_0 = Array3val(self.arr_t_0, {}, 0)
self.const_0_0 = Bits3val(Bits3t(64, 0), 0, 0)
self.const_1_0 = Bits3val(Bits3t(1, 0), 1, 1)
class FloattVal():
"""
Class for value of `Bits3t` type
:ivar ~._dtype: reference on type of this value
:ivar ~.val: always unsigned representation int value
:ivar ~.vld_mask: always unsigned value of the mask, if bit in mask is '0'
the corresponding bit in val is invalid
"""
_BOOL = Bits3t(1)
def __init__(self, t: Floatt, val: Tuple[int, int, int], vld_mask: int):
if not isinstance(t, Floatt):
raise TypeError(t)
if len(val) != 3:
raise TypeError(val)
for x in val:
if not isinstance(x, int):
raise TypeError(val)
assert val[1] >= 0
if type(vld_mask) != int:
raise TypeError(vld_mask)
self._dtype = t
self.val = val
self.vld_mask = vld_mask
def __copy__(self):
return self.__class__(self._dtype, self.val, self.vld_mask)
def to_py(self) -> int:
return int(self)
def _is_full_valid(self) -> bool:
"""
:return: True if all bits in value are valid
"""
return self.vld_mask == self._dtype.all_mask()
def __int__(self) -> int:
"int(self)"
return int(self.__float__())
def __bool__(self) -> bool:
"bool(self)"
return bool(self.__int__())
def __float__(self) -> float:
if not self._is_full_valid():
raise ValidityError()
sign, mantisa, exponent = self.val
mantisa = float(mantisa)
mantisa *= (2**(exponent - self._dtype.mantisa_w))
if sign:
return mantisa * -1.0
else:
return mantisa
def __hash__(self):
return hash((self._dtype, self.val, self.vld_mask))
def _is(self, other):
"""check if other is object with same values"""
return isinstance(other, FloattVal)\
and self._dtype == other._dtype\
and self.val == other.val\
and self.vld_mask == other.vld_mask
def __neg__(self):
"Operator -x."
t = self._dtype
if not self.vld_mask:
return t.from_py(None)
elif self._dtype._is_float_32():
return t.from_py(float(self))
else:
raise NotImplementedError()
def _eq(self, other):
return self._BOOL.from_py(int(self.val == other.val),
vld_mask=self.vld_mask & other.vld_mask)
def __ne__(self, other):
return self._BOOL.from_py(int(self.val != other.val),
vld_mask=self.vld_mask & other.vld_mask)
def __req__(self, other: int) -> "Bits3val":
"Operator ==."
return self._dtype.from_py(other).__eq__(self)
def __rne__(self, other: int) -> "Bits3val":
"Operator !=."
return self._dtype.from_py(other).__ne__(self)
def __lt__(self, other: Union[int, "Bits3val"]) -> "Bits3val":
"Operator <."
return FloattVal__cmp_op(self, other, lt)
def __rlt__(self, other: int) -> "Bits3val":
"Operator <."
return FloattVal__cmp_op(self._dtype.from_py(other), self, lt)
def __gt__(self, other: Union[int, "Bits3val"]) -> "Bits3val":
"Operator >."
return FloattVal__cmp_op(self, other, gt)
def __rgt__(self, other: int) -> "Bits3val":
"Operator >."
return FloattVal__cmp_op(self._dtype.from_py(other), self, gt)
def __ge__(self, other: Union[int, "Bits3val"]) -> "Bits3val":
"Operator >=."
return FloattVal__cmp_op(self, other, ge)
def __rge__(self, other: int) -> "Bits3val":
"Operator >=."
return FloattVal__cmp_op(self._dtype.from_py(other), self, ge)
def __le__(self, other: Union[int, "Bits3val"]) -> "Bits3val":
"Operator <=."
return FloattVal__cmp_op(self, other, le)
def __rle__(self, other: int) -> "Bits3val":
"Operator <=."
return FloattVal__cmp_op(self._dtype.from_py(other), self, le)
def __add__(self, other):
return FloattVal__arith_op(self, other, add)
def __radd__(self, other):
return FloattVal__cmp_op(self._dtype.from_py(other), self, add)
def __sub__(self, other):
return FloattVal__arith_op(self, other, sub)
def __rsub__(self, other):
return FloattVal__cmp_op(self._dtype.from_py(other), self, sub)
def __mul__(self, other):
return FloattVal__arith_op(self, other, mul)
def __rmul__(self, other):
return FloattVal__cmp_op(self._dtype.from_py(other), self, mul)
def __truediv__(self, other):
return FloattVal__arith_op(self, other, truediv)
def __rtruediv__(self, other):
return FloattVal__cmp_op(self._dtype.from_py(other), self, truediv)
#!/usr/bin/env python3
# -*- coding: UTF-8 -*-
import unittest
from pyMathBitPrecise.bits3t import Bits3t
from tests.bits3tBaseTC import uint8_t
BIT = Bits3t(1, name="bit")
def vec(val, w):
t = Bits3t(w)
return t.from_py(val)
class BitsSlicingTC(unittest.TestCase):
def test_slice_bits(self):
v128 = uint8_t.from_py(128)
v1 = uint8_t.from_py(1)
with self.assertRaises(IndexError):
self.assertEqual(v128[8], 1)
self.assertTrue(v128[7]._eq(BIT.from_py(1)))
self.assertTrue(v128[1]._eq(BIT.from_py(0)))
self.assertTrue(v128[0]._eq(BIT.from_py(0)))
with self.assertRaises(IndexError):
v128[-1]
class BasicRtlSimProxy():
"""
Signal proxy which manages the access to a memory in simulation
:ivar ~.callbacks: list of sim processes which will be waken up if signal value is updated
:ivar ~.sim: main simulator
:ivar ~.name: name of property which is this proxy stored in on parent
:ivar ~._name: signal name which was used in HDL
:ivar ~._dtype: data type of this signal
:ivar ~._origin: the object which was this proxy generated from
:ivar ~._ag: agent which controlls this proxy
:ivar ~.parent: parent object
:ivar ~.def_val: value used for initialization of value (done on sim. startup)
:ivar ~.val: actual value of signal
:ivar ~.val_next: place for metainformations about next update
"""
__slots__ = ["callbacks", "sim", "name", "_name", "parent",
"_dtype", "_origin", "_ag",
"def_val", "val", "val_next",
"simRisingSensProcs", "simFallingSensProcs", "simSensProcs"]
BIT_t = Bits3t(1, False)
def __init__(self, sim: "BasicRtlSimulator", parent, name, dtype, def_val):
self.callbacks = []
self.sim = sim
self.parent = parent
self.def_val = def_val
self.val = dtype.from_py(None)
self.val_next = None
# properties used for simplified associations and debug in python
self.name = name # physical name
self._name = name # logical name
self._dtype = dtype # type notation for python
self._origin = None # signal object which this proxy substitutes
self._ag = None # simulation agent which drive or monitor this signal
self.simRisingSensProcs = set()
self.simFallingSensProcs = set()
self.simSensProcs = set()
def init_def_val(self, *args, **kwargs):
self.def_val = self._dtype.from_py(*args, **kwargs)
return self
def read(self):
assert self.sim.read_only_not_write_only
return self.val.__copy__()
def write(self, val):
assert not self.sim.read_only_not_write_only
t = getattr(val, "_dtype", None)
if t is None:
val = self._dtype.from_py(val)
else:
val = self._dtype.from_py(
val.val,
min(val.vld_mask,
self._dtype.all_mask())
)
if valueHasChanged(self.val, val):
self.val = val
self._propagate_changes(None)
def wait(self, cb):
self.callbacks.append(cb)
self.sim.signals_checked_for_change.add(cb)
def _apply_update(self, valUpdater):
"""
Method called by simulator to update new value for this object
"""
dirty_flag, new_val = valUpdater(self.val)
assert new_val._dtype == self._dtype, (self, self.sim.time, new_val._dtype, self._dtype)
if dirty_flag:
self.val = new_val
self._propagate_changes(valUpdater)
def _propagate_changes(self, valUpdater):
v = self.val
sim = self.sim
sim._updated_in_this_step.add(self)
log = sim.logChange
if log:
log(sim.time, self, v, valUpdater)
log = sim.logPropagation
if log:
log(sim, self, self.simSensProcs)
# # run all sensitive processes
for p in self.simSensProcs:
sim._add_hdl_proc_to_run(self, p)
# run write callbacks we have to create new list to allow
# registering of new call backs in callbacks
self.sim.pending_event_list.extend(self.callbacks)
self.callbacks.clear()
if self.simRisingSensProcs:
if v.val or not v.vld_mask:
if log:
log(sim, self, self.simRisingSensProcs)
for p in self.simRisingSensProcs:
sim._add_hdl_proc_to_run(self, p)
if self.simFallingSensProcs:
if not v.val or not v.vld_mask:
if log:
log(sim, self, self.simFallingSensProcs)
for p in self.simFallingSensProcs:
sim._add_hdl_proc_to_run(self, p)
def _onRisingEdge(self):
v = self.val
is_rising = self in self.sim._updated_in_this_step\
and (v.val or not v.vld_mask)
return self.BIT_t.from_py(int(is_rising), int(bool(v.vld_mask)))
def _onFallingEdge(self):
v = self.val
is_falling = self in self.sim._updated_in_this_step\
and (not v.val or not v.vld_mask)
return self.BIT_t.from_py(int(is_falling), int(bool(v.vld_mask)))
def __getitem__(self, index):
if not isinstance(self._dtype, Array3t):
raise TypeError("%r is not iterable because it uses type %r"
% (self, self._dtype))
elif index < 0 or index >= self._dtype.size:
raise IndexError(self._dtype.size, index)
else:
return BasicRtlSimProxyArrItem(self, index)
def __len__(self):
if not isinstance(self._dtype, Array3t):
raise TypeError("%r is not iterable because it uses type %r"
% (self, self._dtype))
else:
return self._dtype.size
def __repr__(self):
return f"<{self.__class__.__name__:s} {self.parent}.{self.name:s} {self.val}->{self.val_next}>"
def __init__(self, sim: "BasicRtlSimulator", name="Showcase0"):
BasicRtlSimModel.__init__(self, sim, name=name)
# ports
self.io.a = BasicRtlSimProxy(sim, self, "a", Bits3t(32, 0), None)
self.io.b = BasicRtlSimProxy(sim, self, "b", Bits3t(32, 1), None)
self.io.c = BasicRtlSimProxy(sim, self, "c", Bits3t(32, 0), None)
self.io.clk = BasicRtlSimProxy(sim, self, "clk", Bits3t(1, 0), None)
self.io.cmp_0 = BasicRtlSimProxy(sim, self, "cmp_0", Bits3t(1, 0),
None)
self.io.cmp_1 = BasicRtlSimProxy(sim, self, "cmp_1", Bits3t(1, 0),
None)
self.io.cmp_2 = BasicRtlSimProxy(sim, self, "cmp_2", Bits3t(1, 0),
None)
self.io.cmp_3 = BasicRtlSimProxy(sim, self, "cmp_3", Bits3t(1, 0),
None)
self.io.cmp_4 = BasicRtlSimProxy(sim, self, "cmp_4", Bits3t(1, 0),
None)
self.io.cmp_5 = BasicRtlSimProxy(sim, self, "cmp_5", Bits3t(1, 0),
None)
self.io.contOut = BasicRtlSimProxy(sim, self, "contOut", Bits3t(32, 0),
None)
self.io.d = BasicRtlSimProxy(sim, self, "d", Bits3t(32, 0), None)
self.io.e = BasicRtlSimProxy(sim, self, "e", Bits3t(1, 0), None)
self.io.f = BasicRtlSimProxy(sim, self, "f", Bits3t(1, 0), None)
self.io.fitted = BasicRtlSimProxy(sim, self, "fitted", Bits3t(16, 0),
None)
self.io.g = BasicRtlSimProxy(sim, self, "g", Bits3t(8, 0), None)
self.io.h = BasicRtlSimProxy(sim, self, "h", Bits3t(8, 0), None)
self.io.i = BasicRtlSimProxy(sim, self, "i", Bits3t(2, 0), None)
self.io.j = BasicRtlSimProxy(sim, self, "j", Bits3t(8, 0), None)
self.io.k = BasicRtlSimProxy(sim, self, "k", Bits3t(32, 0), None)
self.io.out = BasicRtlSimProxy(sim, self, "out", Bits3t(1, 0), None)
self.io.output = BasicRtlSimProxy(sim, self, "output", Bits3t(1, 0),
None)
self.io.rst_n = BasicRtlSimProxy(sim, self, "rst_n", Bits3t(1, 0),
None)
self.io.sc_signal = BasicRtlSimProxy(sim, self, "sc_signal",
Bits3t(8, 0), None)
# internal signals
self.const_private_signal = Bits3val(Bits3t(32, 0), 123, 4294967295)
self.io.fallingEdgeRam = BasicRtlSimProxy(sim, self, "fallingEdgeRam",
self.arr_t_0, None)
self.io.r = BasicRtlSimProxy(sim, self, "r", Bits3t(1, 0),
Bits3val(Bits3t(1, 0), 0, 1))
self.io.r_0 = BasicRtlSimProxy(sim, self, "r_0", Bits3t(2, 0),
Bits3val(Bits3t(2, 0), 0, 3))
self.io.r_1 = BasicRtlSimProxy(sim, self, "r_1", Bits3t(2, 0),
Bits3val(Bits3t(2, 0), 0, 3))
self.io.r_next = BasicRtlSimProxy(sim, self, "r_next", Bits3t(1, 0),
None)
self.io.r_next_0 = BasicRtlSimProxy(sim, self, "r_next_0",
Bits3t(2, 0), None)
self.io.r_next_1 = BasicRtlSimProxy(sim, self, "r_next_1",
Bits3t(2, 0), None)
self.rom = Array3val(
self.arr_t_1, {
0: Bits3val(Bits3t(8, 0), 0, 255),
1: Bits3val(Bits3t(8, 0), 1, 255),
2: Bits3val(Bits3t(8, 0), 2, 255),
3: Bits3val(Bits3t(8, 0), 3, 255)
}, 1)
self.const_4_0 = Bits3val(Bits3t(32, 0), 4, 4294967295)
self.const_4_1 = Bits3val(Bits3t(32, 1), 4, 4294967295)
self.const_0 = Array3val(self.arr_t_0, {}, 0)
self.const_0_0 = Bits3val(Bits3t(32, 0), 0, 0)
self.const_1 = slice(8, 0, -1)
self.const_0_1 = Bits3val(Bits3t(24, 0), 0, 16777215)
self.const_2 = slice(16, 0, -1)
self.const_1_0 = Bits3val(Bits3t(32, 1), 1, 4294967295)
self.const_0_2 = Bits3val(Bits3t(32, 1), 0, 4294967295)
self.const_3 = slice(6, 0, -1)
self.const_0_3 = Bits3val(Bits3t(8, 0), 0, 0)
self.const_2_0 = Bits3val(Bits3t(32, 1), 2, 4294967295)
self.const_1_1 = Bits3val(Bits3t(1, 0), 1, 1)
self.const_0_4 = Bits3val(Bits3t(8, 0), 0, 255)
self.const_1_2 = Bits3val(Bits3t(8, 0), 1, 255)
self.const_2_1 = Bits3val(Bits3t(8, 0), 2, 255)
self.const_0_5 = Bits3val(Bits3t(1, 0), 0, 1)
self.const_0_6 = Bits3val(Bits3t(1, 0), 0, 0)
self.const_0_7 = Bits3val(Bits3t(2, 0), 0, 0)
self.const_0_8 = Bits3val(Bits3t(2, 0), 0, 3)
self.const_1_3 = Bits3val(Bits3t(32, 0), 1, 4294967295)
self.const_2_2 = Bits3val(Bits3t(32, 0), 2, 4294967295)
self.const_3_0 = Bits3val(Bits3t(32, 0), 3, 4294967295)
self.const_3_1 = Bits3val(Bits3t(8, 0), 3, 255)
self.const_4_2 = Bits3val(Bits3t(8, 0), 4, 255)