def test_sub_field_non_exist():
bd = bdl(a=(uw(8), False), b=(sw(8), False))
sf = SubField(n("bd", bd), "c", uw(8))
assert not check(sf)
bd = bdl(a=(bdl(c=(uw(8), True)), False), b=(sw(8), False))
sf = SubField(n("bd", bd), "c", bdl(c=(uw(8), True)))
assert not check(sf)
def test_sub_field_type_wrong():
bd = bdl(a=(uw(8), False), b=(sw(8), False))
sf = SubField(n("bd", bd), "a", sw(8))
assert not check(sf)
bd = bdl(a=(bdl(c=(uw(8), True)), False), b=(sw(8), False))
sf = SubField(n("bd", bd), "a", bdl(c=(uw(9), True)))
assert not check(sf)
def test_type_eq():
assert equal(UnknownType(), UnknownType())
assert equal(ClockType(), ClockType())
assert equal(uw(10), uw(10))
assert equal(sw(10), sw(10))
assert equal(vec(uw(10), 8), vec(uw(10), 8))
assert equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), True)),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), True)))
def test_sub_field_basis():
bd = bdl(a=(uw(8), False), b=(sw(8), False))
sf = SubField(n("bd", bd), "a", uw(8))
assert check(sf)
serialize_equal(sf, "bd.a")
bd = bdl(a=(bdl(c=(uw(8), True)), False), b=(sw(8), False))
sf = SubField(n("bd", bd), "a", bdl(c=(uw(8), True)))
assert check(sf)
serialize_equal(sf, "bd.a")
def test_sub_access_non_vector():
sa = SubAccess(n("vc", uw(8)), u(2, w(3)), uw(8))
assert not check(sa)
sa = SubAccess(n("vc", bdl(a=(vec(uw(8), 10), True))),
u(2, w(3)), vec(uw(8), 10))
assert not check(sa)
def test_write_port_clock_wrong():
mem_ref = n("m", vec(uw(8), 10))
mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", uw(1)))
assert not check(mw)
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), u(0, w(1)))
assert not check(mw)
def test_memory_basis():
mem = DefMemory("m", vec(uw(8), 10))
assert check(mem)
serialize_stmt_equal(mem, 'cmem m : UInt<8>[10]')
mem = DefMemory("m", vec(bdl(a=(uw(8), False)), 10))
assert check(mem)
serialize_stmt_equal(mem, 'cmem m : {a : UInt<8>}[10]')
def test_read_port_mem_wrong():
mem_ref = n("m", bdl(a=(vec(uw(8), 10), False)))
mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert not check(mr)
mem_ref = n("m", uw(9))
mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert not check(mr)
def test_read_port_clock_wrong():
mem_ref = n("m", vec(uw(8), 10))
mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", uw(1)))
assert not check(mr)
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), u(0, w(1)))
assert not check(mr)
def test_write_port_mem_wrong():
mem_ref = n("m", bdl(a=(vec(uw(8), 10), False)))
mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert not check(mw)
mem_ref = n("m", uw(9))
mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert not check(mw)
def test_wire_basis():
wire = DefWire("w1", uw(8))
assert check(wire)
serialize_stmt_equal(wire, 'wire w1 : UInt<8>')
wire = DefWire("w2", bdl(a=(uw(8), True), b=(sw(8), False)))
assert check(wire)
serialize_stmt_equal(wire, 'wire w2 : {flip a : UInt<8>, b : SInt<8>}')
def test_write_port_index_wrong():
mem_ref = n("m", vec(uw(8), 10))
mw = DefMemWritePort("mw", mem_ref, s(2, w(8)), n("clock", ClockType()))
assert not check(mw)
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mw = DefMemWritePort("mw", mem_ref, n("a", vec(uw(1), 10)),
n("clock", ClockType()))
assert not check(mw)
def test_read_port_index_wrong():
mem_ref = n("m", vec(uw(8), 10))
mr = DefMemReadPort("mr", mem_ref, s(2, w(8)), n("clock", ClockType()))
assert not check(mr)
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mr = DefMemReadPort("mr", mem_ref, n("a", vec(uw(1), 10)),
n("clock", ClockType()))
assert not check(mr)
def test_read_port_basis():
mem_ref = n("m", vec(uw(8), 10))
mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert check(mr)
serialize_stmt_equal(mr, 'read mport mr = m[UInt<8>("h2")], clock')
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert check(mr)
serialize_stmt_equal(mr, 'read mport mr = m[a], clock')
def test_write_port_basis():
mem_ref = n("m", vec(uw(8), 10))
mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType()))
assert check(mw)
serialize_stmt_equal(mw, 'write mport mw = m[UInt<8>("h2")], clock')
mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10))
mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), n("clock", ClockType()))
assert check(mw)
serialize_stmt_equal(mw, 'write mport mw = m[a], clock')
def test_type_neq():
assert not equal(UnknownType(), ClockType())
assert not equal(UnknownType(), uw(10))
assert not equal(UnknownType(), sw(10))
assert not equal(UnknownType(), vec(uw(10), 8))
assert not equal(UnknownType(), vec(sw(10), 8))
assert not equal(UnknownType(),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(ClockType(), UnknownType())
assert not equal(ClockType(), uw(10))
assert not equal(ClockType(), sw(10))
assert not equal(ClockType(), vec(uw(10), 8))
assert not equal(ClockType(), vec(sw(10), 8))
assert not equal(ClockType(),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(uw(10), UnknownType())
assert not equal(uw(10), ClockType())
assert not equal(uw(10), uw(8))
assert not equal(uw(10), sw(10))
assert not equal(uw(10), sw(10))
assert not equal(uw(10), vec(uw(10), 8))
assert not equal(uw(10), vec(sw(10), 8))
assert not equal(uw(10),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(sw(10), UnknownType())
assert not equal(sw(10), ClockType())
assert not equal(sw(10), sw(8))
assert not equal(sw(10), uw(10))
assert not equal(sw(10), uw(10))
assert not equal(sw(10), vec(uw(10), 8))
assert not equal(sw(10), vec(sw(10), 8))
assert not equal(sw(10),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(vec(uw(10), 8), UnknownType())
assert not equal(vec(uw(10), 8), ClockType())
assert not equal(vec(uw(10), 8), sw(8))
assert not equal(vec(uw(10), 8), uw(10))
assert not equal(vec(uw(10), 8), uw(10))
assert not equal(vec(uw(10), 8), vec(uw(8), 8))
assert not equal(vec(uw(10), 8), vec(uw(10), 9))
assert not equal(vec(uw(10), 8), vec(sw(10), 8))
assert not equal(vec(uw(10), 8),
bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
UnknownType())
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
ClockType())
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
sw(8))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
uw(10))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
uw(10))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
vec(sw(10), 8))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
bdl(a=(vec(uw(10), 8), True), b=(uw(10), False)))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
bdl(a=(vec(uw(10), 2), False), b=(uw(10), False)))
assert not equal(bdl(a=(uw(3), False), b=(uw(10), False)),
bdl(a=(uw(3), False), b=(uw(10), False), c=(sw(2), True)))
assert not equal(bdl(a=(vec(uw(10), 8), False), b=(uw(10), False)),
bdl(b=(uw(10), False), a=(vec(uw(10), 8), False)))
def test_sub_index_non_vector():
si = SubIndex(n("vc", uw(8)), 5, uw(1))
assert not check(si)
si = SubIndex(n("vc", bdl(a=(vec(uw(8), 10), True))), 19, vec(uw(8), 10))
assert not check(si)
def test_sub_field_not_bundle():
sf = SubField(n("bd", uw(8)), "c", uw(8))
assert not check(sf)
sf = SubField(n("bd", vec(uw(8), 32)), "c", bdl(c=(uw(8), True)))
assert not check(sf)
def test_memory_type_wrong():
mem = DefMemory("m", bdl(a=(vec(uw(8), 10), False)))
assert not check(mem)
mem = DefMemory("m", uw(9))
assert not check(mem)