def write_access(self, address, data):
bs = BitSequence(1, msb=False, length=16) # Bits 15:0 -> Count=1
bs.append(BitSequence(address, msb=False,
length=32)) # bits 47:16 -> 32-bit Address
bs.append(
BitSequence(ADV_DBG_IF_WB_CMD_BURST_WRITE_32, msb=False,
length=4)) # Command
bs.append(BitSequence(0, msb=True, length=1)) # Bit 52
self.jtag.write_dr(bs)
# High-speed mode - no status bit
# Start bit
bs = BitSequence(1, msb=False, length=1)
bs.append(BitSequence(data, msb=False, length=32)) # Data
# first word of a burst : crc_in = 0xFFFFFFFF
crc = self.compute_crc(data_in=data, crc_in=0xFFFFFFFF, length_bits=32)
bs.append(BitSequence(crc, msb=False, length=32)) # CRC
self.jtag.change_state('shift_dr')
self.jtag.write(bs)
match = self.jtag.read(1)
self.jtag.go_idle()
return int(match) == 1
def fetch_data(self):
if len(self.bits_in_read_queue) > 0:
length = self.bits_in_read_queue.popleft()
bs = BitSequence()
byte_count = length // 8
pos = 8 * byte_count
bit_count = length - pos
if byte_count:
data = self._ftdi.read_data_bytes(byte_count, 4)
if not data:
raise JtagError('Unable to read data from FTDI')
byteseq = BitSequence(bytes_=data, length=8 * byte_count)
# print("RW IN %s" % byteseq)
bs.append(byteseq)
# print("pop %d bytes" % byte_count)
if bit_count:
data = self._ftdi.read_data_bytes(1, 4)
if not data:
raise JtagError('Unable to read data from FTDI')
byte = data[0]
# need to shift bits as they are shifted in from the MSB in FTDI
byte >>= 8 - bit_count
bitseq = BitSequence(byte, length=bit_count)
bs.append(bitseq)
# print("pop %d bits" % bit_count)
if len(bs) != length:
raise ValueError("Internal error")
return bs
return None
def shift_register(self, out, use_last=False):
"""Shift a BitSequence into the current register and retrieve the
register output"""
if not isinstance(out, BitSequence):
return JtagError('Expect a BitSequence')
length = len(out)
if use_last:
(out, self._last) = (out[:-1], int(out[-1]))
byte_count = len(out) // 8
pos = 8 * byte_count
bit_count = len(out) - pos
if not byte_count and not bit_count:
raise JtagError("Nothing to shift")
if byte_count:
blen = byte_count - 1
# print("RW OUT %s" % out[:pos])
cmd = array('B',
(Ftdi.RW_BYTES_PVE_NVE_LSB, blen, (blen >> 8) & 0xff))
cmd.extend(out[:pos].tobytes(msby=True))
self._stack_cmd(cmd)
# print("push %d bytes" % byte_count)
if bit_count:
# print("RW OUT %s" % out[pos:])
cmd = array('B', (Ftdi.RW_BITS_PVE_NVE_LSB, bit_count - 1))
cmd.append(out[pos:].tobyte())
self._stack_cmd(cmd)
# print("push %d bits" % bit_count)
self.sync(
) # we cannot skip sync here, because we expect data to be returned from MPSSE
bs = BitSequence()
byte_count = length // 8
pos = 8 * byte_count
bit_count = length - pos
if byte_count:
data = self._ftdi.read_data_bytes(byte_count, 4)
if not data:
raise JtagError('Unable to read data from FTDI')
byteseq = BitSequence(bytes_=data, length=8 * byte_count)
# print("RW IN %s" % byteseq)
bs.append(byteseq)
# print("pop %d bytes" % byte_count)
if bit_count:
data = self._ftdi.read_data_bytes(1, 4)
if not data:
raise JtagError('Unable to read data from FTDI')
byte = data[0]
# need to shift bits as they are shifted in from the MSB in FTDI
byte >>= 8 - bit_count
bitseq = BitSequence(byte, length=bit_count)
bs.append(bitseq)
# print("pop %d bits" % bit_count)
if len(bs) != length:
raise ValueError("Internal error")
return bs
def read(self, length):
"""Read out a sequence of bits from TDO"""
byte_count = length // 8
bit_count = length - 8 * byte_count
bs = BitSequence()
if byte_count:
bytes_ = self._read_bytes(byte_count)
bs.append(bytes_)
if bit_count:
bits = self._read_bits(bit_count)
bs.append(bits)
return bs
def read(self, length):
"""Read out a sequence of bits from TDO"""
byte_count = length // 8
bit_count = length - 8 * byte_count
bs = BitSequence()
if byte_count:
bytes = self._read_bytes(byte_count)
bs.append(bytes)
if bit_count:
bits = self._read_bits(bit_count)
bs.append(bits)
return bs
def shift_register(self, out, use_last=False):
"""Shift a BitSequence into the current register and retrieve the
register output"""
if not isinstance(out, BitSequence):
return JtagError('Expect a BitSequence')
length = len(out)
if use_last:
(out, self._last) = (out[:-1], int(out[-1]))
byte_count = len(out)//8
pos = 8*byte_count
bit_count = len(out)-pos
if not byte_count and not bit_count:
raise JtagError("Nothing to shift")
if byte_count:
blen = byte_count-1
#print "RW OUT %s" % out[:pos]
cmd = Array('B', [Ftdi.RW_BYTES_PVE_NVE_LSB, blen, (blen>>8)&0xff])
cmd.extend(out[:pos].tobytes(msby=True))
self._stack_cmd(cmd)
#print "push %d bytes" % byte_count
if bit_count:
#print "RW OUT %s" % out[pos:]
cmd = Array('B', [Ftdi.RW_BITS_PVE_NVE_LSB, bit_count-1])
cmd.append(out[pos:].tobyte())
self._stack_cmd(cmd)
#print "push %d bits" % bit_count
self.sync()
bs = BitSequence()
byte_count = length//8
pos = 8*byte_count
bit_count = length-pos
if byte_count:
data = self._ftdi.read_data_bytes(byte_count, 4)
if not data:
raise JtagError('Unable to read data from FTDI')
byteseq = BitSequence(bytes_=data, length=8*byte_count)
#print "RW IN %s" % byteseq
bs.append(byteseq)
#print "pop %d bytes" % byte_count
if bit_count:
data = self._ftdi.read_data_bytes(1, 4)
if not data:
raise JtagError('Unable to read data from FTDI')
byte = data[0]
# need to shift bits as they are shifted in from the MSB in FTDI
byte >>= 8-bit_count
bitseq = BitSequence(byte, length=bit_count)
bs.append(bitseq)
#print "pop %d bits" % bit_count
if len(bs) != length:
raise AssertionError("Internal error")
#self._ftdi.validate_mpsse()
return bs
def shift_register(self, out, use_last=False):
if len(out) == 0:
return bytearray()
if isinstance(out, tuple):
out = BitSequence(bytes_=out[1])[:out[0]]
elif isinstance(out, bytearray):
out = BitSequence(bytes_=out)
elif not isinstance(out, BitSequence):
raise Exception('Expect a BitSequence')
length = len(out)
if use_last:
(out, self._last) = (out[:-1], int(out[-1]))
byte_count = len(out) // 8
pos = 8 * byte_count
bit_count = len(out) - pos
if not byte_count and not bit_count:
raise Exception("Nothing to shift")
if byte_count:
blen = byte_count - 1
cmd = array('B',
(Ftdi.RW_BYTES_PVE_NVE_LSB, blen, (blen >> 8) & 0xff))
cmd.extend(out[:pos].tobytes(msby=True))
self._stack_cmd(cmd)
if bit_count:
cmd = array('B', (Ftdi.RW_BITS_PVE_NVE_LSB, bit_count - 1))
cmd.append(out[pos:].tobyte())
self._stack_cmd(cmd)
self._sync()
bs = BitSequence()
byte_count = length // 8
pos = 8 * byte_count
bit_count = length - pos
if byte_count:
data = self._ftdi.read_data_bytes(byte_count, 4)
if not data:
raise Exception('Unable to read data from FTDI')
byteseq = BitSequence(bytes_=data, length=8 * byte_count)
bs.append(byteseq)
if bit_count:
data = self._ftdi.read_data_bytes(1, 4)
if not data:
raise Exception('Unable to read data from FTDI')
byte = data[0]
# need to shift bits as they are shifted in from the MSB in FTDI
byte >>= 8 - bit_count
bitseq = BitSequence(byte, length=bit_count)
bs.append(bitseq)
assert len(bs) == length
return bytearray(bs.tobytes())
def read_access(self, address):
error = False
bs = BitSequence(1, msb=False, length=16) # Bits 15:0 -> Count=1
bs.append(BitSequence(address, msb=False,
length=32)) # bits 47:16 -> 32-bit Address
bs.append(
BitSequence(ADV_DBG_IF_WB_CMD_BURST_READ_32, msb=False,
length=4)) # Command
bs.append(BitSequence(0, msb=True, length=1)) # Bit 52
self.jtag.write_dr(bs)
# Now shift outputs
self.jtag.change_state('shift_dr')
# Read status bit
seq = self.jtag.read(2)
status = 0
while status == 0:
status = self.jtag.read(1)[0]
data = int(self.jtag.read(32))
crc = int(self.jtag.read(32))
# first word of a burst : crc_in = 0xFFFFFFFF
expected_crc = self.compute_crc(data_in=data,
length_bits=32,
crc_in=0xFFFFFFFF)
if crc != expected_crc:
print(
"-E- CRC error detected Data : {0:#010x}, CRC : {1:#010x} Computed CRC : {2:#010x}"
.format(data, crc, expected_crc))
error = True
self.jtag.go_idle()
return data, error
