Esempio n. 1
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def test_complex(din_delay, dout_delay):
    @gear
    async def test(din, *, chunk_len, num_workers) -> b'din':
        counter = Uint[bitw(chunk_len * chunk_len)](0)
        chunk_pow = chunk_len * chunk_len
        async for arr, last_arr in din:
            if counter >= chunk_pow:
                counter = 0
            if not last_arr:
                yield arr, last_arr
                counter += 1
            if last_arr:
                if counter == chunk_pow - 1:
                    yield arr, last_arr
                else:
                    yield arr, Uint[1](0)
                    counter += 1
                    while counter < chunk_pow - 1 and last_arr:
                        yield [[0] * chunk_len] * num_workers, Uint[1](0)
                        counter += 1

                    yield [[0] * chunk_len] * num_workers, Uint[1](1)

    t = Queue[Array[Array[Uint[4], 2], 2]]
    verif(drv(t=t, seq=[[((1, 2),
                          (2, 3))] * 5]) | delay_rng(din_delay, din_delay),
          f=test(name='dut', chunk_len=2, num_workers=2),
          ref=test(chunk_len=2, num_workers=2),
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 2
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def test_qround_non_default():
    verif(drv(t=Fixp[11, 33], seq=[1, 2, 117]),
          f=qround(name='dut', fract=21),
          ref=qround(fract=21))

    cosim('/dut', 'verilator', outdir='/tmp/qround')
    sim()
Esempio n. 3
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def test_cond_nested_loop(din_delay, dout_delay):
    @gear
    async def test(din: Queue[Bool]) -> Uint[4]:
        a = Uint[4](0)

        i = Uint[4](0)
        while i < 4:
            if i < 2:
                async for d in din:
                    print(f'1: {a}')
                    yield a
                    a += 1
                i = 2
            else:
                async for d in din:
                    print(f'2: {a}')
                    yield a
                    a += 2
                i = 4
            i += 1

    verif(drv(t=Queue[Bool], seq=[[True] * 4, [True], [True], [True] * 4])
          | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    # cosim('/dut', 'verilator', outdir='/tools/home/tmp/shedule', rebuild=True)
    cosim('/dut', 'verilator')
    sim()
Esempio n. 4
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def test_code_unit(lang):
    verif(drv(t=Uint[1], seq=list(range(2))),
          f=code_gear(name='dut', t=Unit),
          ref=code_gear(t=Unit))

    cosim('/dut', 'verilator', lang=lang)
    sim()
Esempio n. 5
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def test_code_unit_to_unit(lang):
    verif(drv(t=Uint[0], seq=[0, 0]),
          f=code_gear(name='dut', t=Unit),
          ref=code_gear(t=Unit))

    cosim('/dut', 'verilator', lang=lang)
    sim()
Esempio n. 6
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def test_cast_union_of_units(lang):
    verif(drv(t=Tuple[Unit, Uint[1]], seq=[(Unit(), 0), (Unit(), 1)]),
          f=cast(name='dut', t=Union[Unit, Unit]),
          ref=code_gear(t=Union[Unit, Unit]))

    cosim('/dut', 'verilator', lang=lang)
    sim()
Esempio n. 7
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def test_double_loop(din_delay, dout_delay):
    @gear
    async def test(stop: Integer) -> b'stop + stop':
        cnt1 = stop.dtype(0)

        async with stop as s:
            last1 = False
            while not last1:
                cnt2 = stop.dtype(0)
                last2 = False
                while not last2:
                    yield cnt1 + cnt2
                    last2 = cnt2 == s
                    cnt2 += 1

                last1 = cnt1 == s
                cnt1 += 1

    verif(drv(t=Uint[4], seq=[2, 4]) | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 8
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def test_signed_cosim(cosim_cls):
    seq = [(0x1, 0x7), (-0x2, 0x7), (0x1, -0x8), (-0x2, -0x8)]

    verif(drv(t=Tuple[Int[2], Int[4]], seq=seq),
          f=add(sim_cls=cosim_cls),
          ref=add(name='ref_model'))

    sim()
Esempio n. 9
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def test_signed(cosim_cls):
    a_seq = [-8, -1, 0, 1, 7]
    b = 5

    verif(drv(t=Int[4], seq=a_seq),
          f=add(b=b, sim_cls=cosim_cls),
          ref=add(b=b, name='ref_model'))

    sim()
Esempio n. 10
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def test_fixp(cosim_cls):
    a_seq = [-8., -1, 0, 1, 7]
    b = Fixp[1, 5](-0.125)

    verif(drv(t=Fixp[4, 6], seq=a_seq),
          f=add(b=b, sim_cls=cosim_cls),
          ref=add(b=b, name='ref_model'))

    sim()
Esempio n. 11
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def test_unsigned(cosim_cls):
    a_seq = [0, 5, 14, 15]
    b = 6

    verif(drv(t=Uint[4], seq=a_seq),
          f=add(b=b, sim_cls=cosim_cls),
          ref=add(b=b, name='ref_model'))

    sim()
Esempio n. 12
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def test_qround_fixp(lang):
    seq = [
        -1.5 - 0.0625, -1.5, -0.5 - 0.0625, -0.5, 0.5 - 0.0625, 0.5,
        1.5 - 0.0625, 1.5
    ]

    verif(drv(t=Fixp[6, 10], seq=seq), f=qround(name='dut'), ref=qround)

    cosim('/dut', 'verilator', lang=lang)
    sim()
Esempio n. 13
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def test_2state(dout_delay):
    @gear
    async def test() -> Bool:
        yield False
        yield True

    verif(f=test(name='dut'),
          ref=test(),
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim(timeout=8)
Esempio n. 14
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def test_directed(
    cosim_cls,
    wr0_delay,
    rd0_delay,
    wr1_delay,
    rd1_delay,
    dout_delay,
    depth,
):
    def wr0_delay_gen():
        for _ in range(depth):
            yield 0

        while True:
            yield wr0_delay

    w_addr = 3
    w_data = 8
    wr_req_t = TWrReq[w_addr, Uint[w_data]]
    rd_req_t = Uint[w_addr]
    req_t = Union[rd_req_t, wr_req_t]

    wr0_req_seq = [(i, i * 2) for i in range(depth)]

    wr0_init_seq = [(i, 0) for i in range(depth)]

    rd0_req_seq = list(range(depth))
    rd1_req_seq = list(range(depth))

    wr0_req = drv(t=wr_req_t, seq=wr0_init_seq + wr0_req_seq) \
        | delay_gen(f=wr0_delay_gen())

    rd0_req = drv(t=Uint[w_addr], seq=rd0_req_seq) \
        | delay_gen(f=iter([depth])) \
        | delay_rng(0, rd0_delay)

    req0 = priority_mux(rd0_req, wr0_req)

    req1 = ccat(drv(t=Uint[w_addr], seq=rd1_req_seq) \
                | req_t.data \
                | delay_gen(f=iter([depth])) \
                | delay_rng(0, rd1_delay)
                , Bool(False)) | req_t

    verif(req0,
          req1,
          f=tdp(name='dut', sim_cls=cosim_cls, depth=depth),
          ref=tdp(depth=depth),
          delays=[delay_rng(0, dout_delay),
                  delay_rng(0, 0)])

    sim()
Esempio n. 15
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def test_code(lang):
    @datagear
    def test(din, *, t) -> b't':
        return code(din, t)

    cast_t = Maybe[Uint[31]]

    verif(drv(t=Uint[32], seq=list(range(10))),
          f=test(name='dut', t=cast_t),
          ref=test(t=cast_t))

    cosim('/dut', 'verilator', lang=lang)
    sim()
Esempio n. 16
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def test_cordic_stage(tmpdir, do_cosim):

    verif(drv(t=Tuple[Int[15], Int[15], Uint[19]],
              seq=[(-4768, 1768, 0xbaba)]),
          f=cordic_stage(i=1,
                         ww=15,
                         pw=20,
                         cordic_angle=Uint[20](0xbaba),
                         name='dut'),
          ref=cordic_stage(i=1, ww=15, pw=20, cordic_angle=Uint[20](0xbaba)))
    if do_cosim:
        cosim('/dut', 'verilator')

    sim(tmpdir)
Esempio n. 17
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def test_state_in_scope(din_delay, dout_delay):
    @gear
    async def test(din: Queue[Uint[4]]) -> Uint[4]:
        async for c, eot in din:
            yield c
            yield c

    verif(drv(t=Queue[Uint[4]], seq=[[2, 6, 10, 14]])
          | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 18
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def test_delay(cosim_cls, din_delay, dout_delay):
    def bitfield(n):
        return [int(digit) for digit in bin(n)[2:]]

    seq = [bitfield(0x73), bitfield(0x00)]
    init = [1, 0]

    dut = get_decoupled_dut(dout_delay, reduce(f=lambda x, y: x ^ y))
    verif(drv(t=Queue[Bool], seq=seq) | delay_rng(din_delay, din_delay),
          drv(t=Uint[8], seq=init),
          f=dut(sim_cls=cosim_cls),
          ref=reduce(name='ref_model', f=lambda x, y: x ^ y),
          delays=[delay_rng(dout_delay, dout_delay)])

    sim()
Esempio n. 19
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def test_din_state(din_delay, dout_delay):
    @gear
    async def test(din: Uint[4]) -> Uint[4]:
        async with din as c:
            yield c

        async with din as c:
            yield c

    verif(drv(t=Uint[4], seq=[1, 2, 3, 4]) | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 20
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def test_leave_looped(din_delay, dout_delay):
    @gear
    async def test(din: Bool) -> Bool:
        c = Bool(True)
        while c:
            async with din as c:
                if c:
                    yield 0
                else:
                    yield 1

    verif(drv(t=Bool, seq=[True, False, False, True]) | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 21
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def test_double_loop_seq_explicit_split(din_delay, dout_delay):
    @gear
    async def test(din: Queue[Uint[4]]) -> Uint[5]:
        async for d, _ in din:
            yield d + 1

        await clk()

        async for d, _ in din:
            yield d + 2

    verif(drv(t=Queue[Uint[4]], seq=[[1, 2, 3] * 2] * 2)
          | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 22
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def test_loop_after_async_with(din_delay, dout_delay):
    @gear
    async def test(din: Uint[4]) -> Uint[4]:
        async with din as d:
            yield 1

        d = 0
        while d < 3:
            async with din as d:
                yield 0

    verif(drv(t=Uint[4], seq=[1, 2, 3, 4, 1, 2, 3, 4])
          | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 23
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def test_basic_loop(din_delay, dout_delay):
    @gear
    async def test(din: Bool) -> Uint[4]:
        a = Uint[4](0)

        c = True
        while c:
            async with din as c:
                yield a
                a += 1

    verif(drv(t=Bool, seq=[True, False, False, True])
          | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 24
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def test_optional_loop(din_delay, dout_delay):
    @gear
    async def test(din: Uint[4]) -> Uint[4]:
        async with din as c:
            if c > 1:
                for i in range(2):
                    yield i
            else:
                for i in range(3):
                    yield i

    verif(drv(t=Uint[4], seq=[1, 2, 3, 4, 1, 2, 3, 4])
          | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 25
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def test_optional_loop_assign(din_delay, dout_delay):
    @gear
    async def test(din: Queue[Bool]) -> Bool:
        flag = False

        async for d, eot in din:
            if d:
                flag = True

        yield flag

    verif(drv(t=Queue[Bool], seq=[[True, False, False, True]])
          | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 26
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def test_socket_rand_cons():
    skip_ifndef('SIM_SOCKET_TEST', 'RANDOM_TEST')

    cnt = 5

    cons = []
    cons.append(randomize(t_din, 'din', eot_cons=['data_size == 20']))
    cons.append(randomize(t_cfg, 'cfg', cons=['cfg < 20', 'cfg > 0']))

    stim = []

    stim.append(drv(t=t_din, seq=rand_seq('din', cnt)))
    stim.append(drv(t=t_cfg, seq=rand_seq('cfg', cnt)))

    verif(*stim,
          f=chop(sim_cls=partial(SimSocket, run=True)),
          ref=chop(name='ref_model'))

    sim(extens=[partial(SVRandSocket, cons=cons)])
Esempio n. 27
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def test_cond_state(din_delay, dout_delay):
    @gear
    async def test(din: Uint[4]) -> Uint[4]:
        async with din as c:
            if c < 12:
                yield 1

            yield 2

            if c > 4:
                yield 3

    verif(drv(t=Uint[4], seq=[2, 6, 10, 14]) | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 28
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def test_qrange(din_delay, dout_delay):
    @gear
    async def test(stop: Integer) -> b'stop':
        cnt = stop.dtype(0)
        last: Bool

        async with stop as s:
            last = False
            while not last:
                last = cnt == s
                yield cnt
                cnt += 1

    verif(drv(t=Uint[4], seq=[2, 4]) | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 29
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def test_double_loop_seq(din_delay, dout_delay):
    @gear
    async def test(din: Uint[4]) -> Uint[4]:
        c = Uint[4](0)
        while c[:1] == 0:
            async with din as c:
                yield c

        c = Uint[4](0)
        while c[:1] == 0:
            async with din as c:
                yield code(2 * c, Uint[4])

    verif(drv(t=Uint[4], seq=[1, 2, 3, 4, 1, 2, 3, 4])
          | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()
Esempio n. 30
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def test_cond_nested_loop_multistate(din_delay, dout_delay):
    @gear
    async def test(din: Queue[Bool]) -> Uint[4]:
        a = Uint[4](0)
        while a < 4:
            if a < 2:
                async for d in din:
                    yield a
                    # Influences above condition, but should not make a
                    # difference while loop is running
                    a += 1
            a += 1

    verif(drv(t=Queue[Bool], seq=[[True] * 4, [True], [True], [True] * 4])
          | delay_rng(din_delay, din_delay),
          f=test(name='dut'),
          ref=test,
          delays=[delay_rng(dout_delay, dout_delay)])

    cosim('/dut', 'verilator')
    sim()