def Gear(self, module):
if module.parent is None:
return False
if module.params.get('__sim__', None) is not None:
cfg = module.params['__sim__']
if isinstance(cfg, dict):
cfg = cfg.copy()
sim = cfg.pop('sim')
cosim(module, sim, **cfg)
else:
cosim(module, cfg)
sim_cls = module.params.get('sim_cls', None)
sim_inst = None
if sim_cls is None:
sim_cls = self.namespace.get(module.definition, None)
if sim_cls:
sim_inst = sim_cls(module)
elif is_simgear_func(module.func):
sim_inst = SimGear(module)
if sim_inst:
self.sim_map[module] = sim_inst
return True
def fir_sim(impl, t_b, seq, do_cosim, target='build/fir'):
# get 'b' factors
b = firwin(8, [0.05, 0.95], width=0.05, pass_zero=False)
b_fixp = [t_b(i) for i in b]
# get result
res = np.convolve(seq, b)
# saturate the results value to filter output type if needed
for i, r in enumerate(res):
res[i] = fixp_sat(t_b, r)
# driving
drv(t=t_b, seq=seq) \
| impl(b=b_fixp) \
| Float \
| check(ref=res[:len(seq)], cmp=fir_compare)
# optionally generate HDL code do co-simulation in verilator
if do_cosim:
cosim(f'{impl}', 'verilator', outdir=target, timeout=1000)
# simulation start
sim(target, check_activity=False)
return res
def iir_sim(impl,
t_coef,
t_in,
t_out,
seq,
target='build/iir',
do_cosim=False):
# create SOS referent filter and factors
sos = signal.butter(N=5,
Wn=30000 / 100000,
btype='lowpass',
analog=False,
output='sos')
# get a,b coefficient from the created filter
a, b = [], []
for s in sos:
b.append(list(s[0:3]))
a.append(list(s[3:]))
# convert coefficient to wanted Fixp type
b = [[t_coef(coef) for coef in section] for section in b]
a = [[t_coef(coef) for coef in section] for section in a]
log.debug(f'Generated B coeff: {b}')
log.debug(f'Generated A coeff: {a}')
gain = [t_in(1)] * len(b)
ref = signal.sosfilt(sos, seq)
# fp_ref = [float(r) for r in ref]
# saturate the results value to filter output type if needed
for i, r in enumerate(ref):
ref[i] = fixp_sat(t_out, float(r))
log.debug(f'Generated sequence: {seq}')
log.debug(f'Refferenc result: {ref}')
drv(t=t_in, seq=seq) \
| impl(a=a, b=b, gain=gain, ogain=t_in(1)) \
| Float \
| check(ref=ref[:len(seq)], cmp=iir_compare)
# optionally generate HDL code do co-simulation in verilator
if do_cosim:
cosim(f'{impl}', 'verilator', outdir=target, timeout=1000)
sim(target, check_activity=False)
return ref
def test_iir_direct(tmpdir, impl, seed, do_cosim):
reg['sim/rand_seed'] = seed
random.seed(reg['sim/rand_seed'])
log.info(
f'Running test_fir_direct tmpdir: {tmpdir}, impl: {impl}, seed: {seed}'
)
reg['sim/clk_freq'] = 100000
t = list(range(reg['sim/clk_freq']))[0:100]
fs = reg['sim/clk_freq']
f1 = 1000
f2 = 70000
seq = []
for n in t:
seq.append(1 * sin(2 * pi * f1 / fs * n) +
0.1 * sin(2 * pi * f2 / fs * n))
sos = signal.butter(N=5,
Wn=30000 / 100000,
btype='lowpass',
analog=False,
output='sos')
a, b = [], []
for s in sos:
b.append(list(s[0:3]))
a.append(list(s[3:]))
t_coef = Fixp[5, 32]
b = [[t_coef(coef) for coef in section] for section in b]
a = [[t_coef(coef) for coef in section] for section in a]
gain = [Fixp[2, 23](1)] * len(b)
ref = signal.sosfilt(sos, seq)
fp_ref = [float(r) for r in ref]
log.debug(f'Generated sequence: {seq}')
drv(t=Fixp[5, 24], seq=seq) \
| impl(a=a, b=b, gain=gain, ogain=Fixp[5, 24](1)) \
| Float \
| check(ref=fp_ref[:len(seq)], cmp=lambda x, y: abs(x - y) < 1e-3)
if do_cosim:
cosim(f'{impl}', 'verilator', outdir=tmpdir, timeout=1000)
sim(tmpdir, check_activity=False)