def test_has_outbound_mergers(self):
import pyhalbe
import pysthal
from pyhalco_common import Enum
import pyhalco_hicann_v2 as C
wafer_c = C.Wafer(33)
gbitlink_c = C.GbitLinkOnHICANN(Enum(0))
fpga_on_wafer_c = C.FPGAOnWafer(Enum(0))
fpga_c = C.FPGAGlobal(fpga_on_wafer_c, wafer_c)
hicann_cs = [
C.HICANNGlobal(h, wafer_c) for h in fpga_c.toHICANNOnWafer()
]
hicann_c = hicann_cs[0]
hicann_on_dnc_c = hicann_c.toHICANNOnWafer().toHICANNOnDNC()
dnc_on_fpga_c = hicann_c.toDNCOnFPGA()
w = pysthal.Wafer()
h = w[hicann_c.toHICANNOnWafer()]
f = w[fpga_on_wafer_c]
self.assertFalse(f.hasOutboundMergers())
f[dnc_on_fpga_c][hicann_on_dnc_c].layer1[
gbitlink_c] = pyhalbe.HICANN.GbitLink.Direction.TO_DNC
self.assertTrue(f.hasOutboundMergers())
def test(self):
wafer = 99999 # a wafer for which no redman data is availale
hicann = 82
neuron_number = 12
marocco = PyMarocco()
marocco.neuron_placement.default_neuron_size(4)
marocco.backend = PyMarocco.Without
marocco.default_wafer = C.Wafer(wafer)
used_hicann = C.HICANNGlobal(C.HICANNOnWafer(Enum(hicann)),
C.Wafer(wafer))
used_hicann # prevent pep8 warning of unused variable
pynn.setup(marocco=marocco)
pop = pynn.Population(1, pynn.IF_cond_exp)
topleft = C.NeuronOnWafer(C.NeuronOnHICANN(X(neuron_number), Y(0)),
C.HICANNOnWafer(Enum(hicann)))
logical_neuron = LogicalNeuron.rectangular(topleft, size=4)
marocco.manual_placement.on_neuron(pop, logical_neuron)
with self.assertRaises(RuntimeError):
pynn.run(0)
pynn.end()
def test_L1_detour_at_side_switch_usage(self):
"""
[155]
191
[223] 224 225 x226x {227}
test detour and predecessor settings at the edge of a wafer
"""
pylogging.set_loglevel(pylogging.get("marocco"),
pylogging.LogLevel.TRACE)
pylogging.set_loglevel(pylogging.get("Calibtic"),
pylogging.LogLevel.ERROR)
self.marocco.persist = '' # or add test suite TestWithRuntime?
runtime = Runtime(self.marocco.default_wafer)
pynn.setup(marocco=self.marocco, marocco_runtime=runtime)
settings = pysthal.Settings.get()
settings.synapse_switches.max_switches_per_column_per_side = 1
settings.crossbar_switches.max_switches_per_row = 1
source = pynn.Population(1, pynn.IF_cond_exp, {})
target1 = pynn.Population(1, pynn.IF_cond_exp, {})
target2 = pynn.Population(1, pynn.IF_cond_exp, {})
proj = pynn.Projection(
source, target1, pynn.AllToAllConnector(weights=1.))
proj = pynn.Projection(
source, target2, pynn.AllToAllConnector(weights=1.))
source_hicann = C.HICANNOnWafer(Enum(227))
target1_hicann = C.HICANNOnWafer(Enum(155))
target2_hicann = C.HICANNOnWafer(Enum(225))
self.marocco.manual_placement.on_hicann(source, source_hicann)
self.marocco.manual_placement.on_hicann(target1, target1_hicann)
self.marocco.manual_placement.on_hicann(target2, target2_hicann)
disabled_hicanns = [226, 263]
wafer = self.marocco.default_wafer
self.marocco.defects.set(pyredman.Wafer(runtime.wafer().index()))
for hicann in C.iter_all(C.HICANNOnWafer):
if hicann.toEnum().value() in disabled_hicanns:
self.marocco.defects.wafer().hicanns().disable(C.HICANNGlobal(hicann, wafer))
continue
pynn.run(0)
pynn.end()
for hicann in runtime.wafer().getAllocatedHicannCoordinates():
h = runtime.wafer()[hicann]
print(hicann, h.check())
self.assertEqual(h.check(), "")
def test_add_to_empty_db(self):
mydb = pyhwdb.database()
fpga_coord = coord.FPGAGlobal(self.FPGA_COORD, self.WAFER_COORD)
hicann_coord = coord.HICANNGlobal(self.HICANN_COORD, self.WAFER_COORD)
with self.assertRaises(IndexError):
mydb.add_fpga_entry(fpga_coord, pyhwdb.FPGAEntry())
with self.assertRaises(IndexError):
mydb.add_hicann_entry(hicann_coord, pyhwdb.HICANNEntry())
def test_CrossbarWriteRead(self):
highspeed = True
hicann_num = 2
ip = self.ip
port = 1701
myPowerBackend = PowerBackend.instance(PowerBackend.VerticalSetup)
myPowerBackend.SetupReticle(ip, port, hicann_num, highspeed, True)
h1 = Handle.HICANN(Coordinate.HICANNGlobal(Enum(0)))
h2 = Handle.HICANN(Coordinate.HICANNGlobal(Enum(1)))
init(h1)
init(h2)
import numpy.random as rd
def create_pattern():
return [[bool(i < 0.5) for i in rd.randint(2, size=4)]
for n in range(64)]
patterns_left = [create_pattern() for n in range(2)]
patterns_right = [create_pattern() for n in range(2)]
# UGLY!
read_pattern = [[True] * 4] * 64
for n, h in enumerate([h1, h2]):
for i in range(0, 64):
set_crossbar_switch_row(h, Coordinate.HLineOnHICANN(i), left,
patterns_left[n][i])
set_crossbar_switch_row(h, Coordinate.HLineOnHICANN(i), right,
patterns_right[n][i])
for n, h in enumerate([h1, h2]):
# left
for i in range(0, 64):
read_pattern[i] = get_crossbar_switch_row(
h, Coordinate.HLineOnHICANN(i), left)
self.assertEqual(patterns_left[n], read_pattern)
# right
for i in range(0, 64):
read_pattern[i] = get_crossbar_switch_row(
h, Coordinate.HLineOnHICANN(i), right)
self.assertEqual(patterns_right[n], read_pattern)
def test_dnc_copy(self):
import copy
wafer_c = C.Wafer(33)
w = pysthal.Wafer(wafer_c)
h_c = C.HICANNGlobal(C.HICANNOnWafer(Enum(297)), wafer_c)
h = w[h_c.toHICANNOnWafer()]
d = w[h_c.toFPGAOnWafer()][h_c.toDNCOnFPGA()]
d2 = copy.deepcopy(d)
self.assertEqual(d, d2)
# change something to ensure that it's not a mere pointer copy
h2 = w[C.HICANNOnWafer(Enum(298))]
self.assertNotEqual(d, d2)
def test_dnc_pickle(self):
import pickle
wafer_c = C.Wafer(33)
w = pysthal.Wafer(wafer_c)
h_c = C.HICANNGlobal(C.HICANNOnWafer(Enum(297)), wafer_c)
h = w[h_c.toHICANNOnWafer()]
d = w[h_c.toFPGAOnWafer()][h_c.toDNCOnFPGA()]
d_str = pickle.dumps(d)
d2 = pickle.loads(d_str)
self.assertEqual(d, d2)
# change something to ensure that it's not a mere pointer copy
h2 = w[C.HICANNOnWafer(Enum(298))]
self.assertNotEqual(d, d2)
def f_hicann(hicann):
"""prints Hicann related variables"""
ghicann = Coordinate.HICANNGlobal(hicann, WAFER)
out = print_hicann(ghicann)
fpga = ghicann.toFPGAOnWafer()
dnc = ghicann.toDNCGlobal()
for coordinate in [fpga, dnc, dnc.toDNCOnFPGA(),
dnc.toPowerCoordinate(), hicann.toHICANNOnDNC()]:
has_id = getattr(coordinate, "id", None)
if has_id:
out += "\t{} ({})\n".format(coordinate, coordinate.toEnum())
else:
out += "\t{}\n".format(coordinate)
try:
import pysthal
db = pysthal.MagicHardwareDatabase()
ip = db.get_fpga_ip(Coordinate.HICANNGlobal(hicann, WAFER))
port = 1700 + dnc.toDNCOnFPGA().value()
out += "\t{} {}".format(ip.to_string(), port)
except Exception:
pass
return out
def test_dijkstra_routing(self):
"""
Integration test for Dijkstra-based L1 routing.
Sets up a convoluted case that requires a convex route (which would
not work using the backbone router).
.------->------+
167 168 169 170 |
206 v
240 241 242 |
^---<------+
"""
pynn.setup(marocco=self.marocco)
source = pynn.Population(1, pynn.IF_cond_exp, {})
target = pynn.Population(1, pynn.IF_cond_exp, {})
proj = pynn.Projection(
source, target, pynn.AllToAllConnector(weights=0.004))
source_hicann = C.HICANNOnWafer(Enum(167))
target_hicann = C.HICANNOnWafer(Enum(240))
self.marocco.manual_placement.on_hicann(source, source_hicann)
self.marocco.manual_placement.on_hicann(target, target_hicann)
allowed_hicanns = [206] + list(range(167, 171)) + list(range(240, 243))
wafer = self.marocco.default_wafer
self.marocco.defects.set(pyredman.Wafer())
for hicann in C.iter_all(C.HICANNOnWafer):
if hicann.toEnum().value() in allowed_hicanns:
continue
self.marocco.defects.wafer().hicanns().disable(C.HICANNGlobal(hicann, wafer))
self.marocco.l1_routing.algorithm(self.marocco.l1_routing.dijkstra)
pynn.run(0)
pynn.end()
results = self.load_results()
synapses = results.synapse_routing.synapses()
self.assertEqual(1, synapses.size())
def run_experiment(self,
marocco,
n_stim,
rate,
poisson=True,
shuffle=False):
"""
runs experiment with `n_stim` SpikeSources, firing at
`rate` Hz, all connected to 1 neuron.
returns a result dictionary, with keys `hicanns` and `fpgas`, each
containing used FPGA/HICANN coords and number of sources mapped per
FPGA/HICANN.
further params:
poisson - if True, use SpikeSourcePoisson, else use SpikeSourceArrays
with regular firing
shuffle - if True, the spike times used for SpikeSourceArray are
shuffled, i.e. they are not sorted. Only valid if
poisson=True)
"""
sim_duration = 200.
marocco.persist = os.path.join(self.temporary_directory, "results.bin")
pynn.setup(marocco=marocco)
exc_pop = pynn.Population(1, pynn.IF_cond_exp, {})
# place target onto a hicann in the center of reticle and at the border of the wafer
# such that hicanns from the same reticle are used with preference (1 reticle -> same fpga)
marocco.manual_placement.on_hicann(
exc_pop, C.HICANNOnWafer(pyhalco_common.Enum(1)))
if poisson:
pop_stim = pynn.Population(n_stim, pynn.SpikeSourcePoisson, {
'rate': rate,
'duration': sim_duration
})
else:
pop_stim = pynn.Population(n_stim, pynn.SpikeSourceArray)
for i in range(n_stim):
isi = 1.e3 / rate
spike_times = np.arange((i + 1) * 1. / n_stim * isi,
sim_duration, isi)
if shuffle:
np.random.shuffle(spike_times)
pop_stim[i:i + 1].set('spike_times', spike_times.tolist())
a2a = pynn.AllToAllConnector(weights=0.001, delays=2.)
pynn.Projection(pop_stim, exc_pop, a2a, target='excitatory')
pynn.run(sim_duration)
results = Marocco.from_file(marocco.persist)
hicanns = {} # count number of stimuli mapped on Hicann
fpgas = {} # count number of stimuli mapped on fpga
for idx in range(len(pop_stim)):
items = list(results.placement.find(pop_stim[idx]))
# stim nrns are only placed once per wafer
self.assertEqual(1, len(items))
address = items[0].address()
hicann_str = str(address.toHICANNOnWafer())
hicanns[hicann_str] = hicanns.get(hicann_str, 0) + 1
hicann_global = C.HICANNGlobal(address.toHICANNOnWafer(),
C.Wafer())
fpga_str = str(hicann_global.toFPGAGlobal())
fpgas[fpga_str] = fpgas.get(fpga_str, 0) + 1
pynn.end()
return dict(hicanns=hicanns, fpgas=fpgas)
#!/usr/bin/env python
"""
exits with 0 if given HICANN has highspeed, with 1 otherwise
"""
import argparse
from pyhalco_common import Enum
import pyhalco_hicann_v2 as C
from pyredman.load import load
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument('--wafer', type=int, required=True, help="Wafer enum")
parser.add_argument('--hicann',
type=int,
required=True,
help="HICANNOnWafer enum")
parser.add_argument('--defects_path',
required=True,
help="path to defects files")
args = parser.parse_args()
wafer_c = C.Wafer(args.wafer)
hicann_c = C.HICANNOnWafer(Enum(args.hicann))
hicann_global_c = C.HICANNGlobal(hicann_c, wafer_c)
fpga_global_c = hicann_global_c.toFPGAGlobal()
backend = load.FpgaWithBackend(args.defects_path, fpga_global_c)
has_highspeed = backend.hslinks().has(hicann_global_c.toHighspeedLinkOnDNC())
exit(not has_highspeed)
#!/usr/bin/env python
import pyhalco_hicann_v2 as C
from pyredman.load import load
backend = load.HicannWithBackend("./", C.HICANNGlobal())
backend.save()
backend = load.WaferWithBackend("./", C.Wafer())
backend.save()
def test_database_access(self):
mydb = pyhwdb.database()
if IS_PYPLUSPLUS:
wafer = pyhwdb.WaferEntry()
wafer_coord = self.WAFER_COORD
wafer.setup_type = self.WAFER_SETUP_TYPE
self.assertFalse(mydb.has_wafer_entry(wafer_coord))
mydb.add_wafer_entry(wafer_coord, wafer)
self.assertTrue(mydb.has_wafer_entry(wafer_coord))
self.assertEqual(mydb.get_wafer_entry(wafer_coord).setup_type, wafer.setup_type)
wafer_coords = mydb.get_wafer_coordinates()
self.assertEqual(len(wafer_coords), 1)
mydb.remove_wafer_entry(wafer_coord)
self.assertFalse(mydb.has_wafer_entry(wafer_coord))
dls_entry = pyhwdb.DLSSetupEntry()
dls_setup_id = self.DLS_SETUP_ID
self.assertFalse(mydb.has_dls_entry(dls_setup_id))
mydb.add_dls_entry(dls_setup_id, dls_entry)
self.assertTrue(mydb.has_dls_entry(dls_setup_id))
mydb.remove_dls_entry(dls_setup_id)
self.assertFalse(mydb.has_dls_entry(dls_setup_id))
if not IS_PYPLUSPLUS:
hxcube_entry = pyhwdb.HXCubeSetupEntry()
hxcube_id = self.HXCUBE_ID
hxcube_entry.hxcube_id = hxcube_id
hxcube_entry.usb_host = "fantasy"
hxcube_entry.usb_serial = "ABACD1243"
fpga_entry = pyhwdb.HXCubeFPGAEntry()
fpga_entry.ip = self.FPGA_IP
wing_entry = pyhwdb.HXCubeWingEntry()
wing_entry.ldo_version = 8
wing_entry.eeprom_chip_serial = 0x987DE
wing_entry.handwritten_chip_serial = 12
wing_entry.chip_revision = 42
fpga_entry.wing = wing_entry
fpga_entry2 = pyhwdb.HXCubeFPGAEntry()
hxcube_entry.fpgas = {0: fpga_entry, 3: fpga_entry2}
self.assertFalse(mydb.has_hxcube_setup_entry(hxcube_id))
mydb.add_hxcube_setup_entry(hxcube_id, hxcube_entry)
self.assertTrue(mydb.has_hxcube_setup_entry(hxcube_id))
mydb.remove_hxcube_setup_entry(hxcube_id)
self.assertFalse(mydb.has_hxcube_setup_entry(hxcube_id))
self.assertEqual(hxcube_entry.get_unique_branch_identifier(12),
"hxcube9fpga0chip12_1")
with self.assertRaises(RuntimeError):
hxcube_entry.get_unique_branch_identifier(108)
if IS_PYPLUSPLUS:
# require wafer entry to write other entry typed into
mydb.add_wafer_entry(wafer_coord, wafer)
fpga = pyhwdb.FPGAEntry()
fpga_coord = coord.FPGAGlobal(self.FPGA_COORD, self.WAFER_COORD)
fpga.ip = self.FPGA_IP
self.assertFalse(mydb.has_fpga_entry(fpga_coord))
mydb.add_fpga_entry(fpga_coord, fpga)
self.assertTrue(mydb.has_fpga_entry(fpga_coord))
self.assertEqual(mydb.get_fpga_entry(fpga_coord).ip, fpga.ip)
mydb.remove_fpga_entry(fpga_coord)
self.assertFalse(mydb.has_fpga_entry(fpga_coord))
reticle = pyhwdb.ReticleEntry()
reticle_coord = coord.DNCGlobal(self.RETICLE_COORD, self.WAFER_COORD)
reticle.to_be_powered = self.RETICLE_TO_BE_POWERED
self.assertFalse(mydb.has_reticle_entry(reticle_coord))
mydb.add_reticle_entry(reticle_coord, reticle)
self.assertTrue(mydb.has_reticle_entry(reticle_coord))
self.assertEqual(mydb.get_reticle_entry(reticle_coord).to_be_powered, reticle.to_be_powered)
mydb.remove_reticle_entry(reticle_coord)
self.assertFalse(mydb.has_reticle_entry(reticle_coord))
# require fpga entry to add hicann entry
mydb.add_fpga_entry(fpga_coord, fpga)
hicann = pyhwdb.HICANNEntry()
hicann_coord = coord.HICANNGlobal(self.HICANN_COORD, self.WAFER_COORD)
hicann.version = self.HICANN_VERSION
self.assertFalse(mydb.has_hicann_entry(hicann_coord))
mydb.add_hicann_entry(hicann_coord, hicann)
self.assertTrue(mydb.has_hicann_entry(hicann_coord))
self.assertEqual(mydb.get_hicann_entry(hicann_coord).version, hicann.version)
mydb.remove_hicann_entry(hicann_coord)
self.assertFalse(mydb.has_hicann_entry(hicann_coord))
# test clear()
mydb.add_hicann_entry(hicann_coord, hicann)
mydb.clear()
self.assertFalse(mydb.has_hicann_entry(hicann_coord))
self.assertFalse(mydb.has_fpga_entry(fpga_coord))
self.assertFalse(mydb.has_wafer_entry(wafer_coord))