def hypothesis_test_harness(s, associativity, clw, num_blocks,
transactions, req, stall_prob, latency,
src_delay, sink_delay, dump_vcd, test_verilog):
cacheSize = (clw * associativity * num_blocks) // 8
mem = rand_mem(addr_min, addr_max)
CacheReqType, CacheRespType = mk_mem_msg(obw, abw, dbw)
MemReqType, MemRespType = mk_mem_msg(obw, abw, clw)
# FL Model to generate expected transactions
model = ModelCache(cacheSize, associativity, 0, CacheReqType,
CacheRespType, MemReqType, MemRespType, mem)
# Grab list of generated transactions
reqs_lst = req.draw(st.lists(gen_reqs(),
min_size=1,
max_size=transactions),
label="requests")
for i in range(len(reqs_lst)):
addr, type_, data, len_ = reqs_lst[i]
if type_ == MemMsgType.WRITE:
model.write(addr, data, i, len_)
else:
# Read something
model.read(addr, i, len_)
msgs = model.get_transactions() # Get FL response
# Prepare RTL test harness
s.run_test(msgs, mem, CacheReqType, CacheRespType, MemReqType,
MemRespType, associativity, cacheSize, stall_prob, latency,
src_delay, sink_delay, dump_vcd, test_verilog, 1)
def test_dmapped_4kb_cache(s, dump_vcd, test_verilog):
msgs = [
# type opq addr len data type opq test len data
req('rd', 0, 0x00000000, 0, 0),
resp('rd', 0x0, 0, 0, 0xa0b0c0d0),
req('rd', 1, 0x00000000, 0, 0),
resp('rd', 0x1, 1, 0, 0xa0b0c0d0),
req('rd', 2, 0x00000000, 0, 0),
resp('rd', 0x2, 1, 0, 0xa0b0c0d0),
]
mem = s.hypo_mem()
MemReqType, MemRespType = mk_mem_msg(obw, abw, 128)
s.run_test(msgs,
mem,
CacheReqType,
CacheRespType,
MemReqType,
MemRespType,
1,
4096,
0,
1,
0,
0,
dump_vcd=dump_vcd,
test_verilog=test_verilog)
def test_2way_hyp1(s, dump_vcd, test_verilog):
msgs = [
req('rd', 0x00, 0x8, 0, 0),
resp('rd', 0x00, 0, 0, 2),
req('wr', 0x01, 0x20, 0, 0),
resp('wr', 0x01, 0, 0, 0),
req('rd', 0x02, 0x8, 0, 0),
resp('rd', 0x02, 1, 0, 2),
req('rd', 0x03, 0, 0, 0),
resp('rd', 0x03, 0, 0, 1),
]
mem = s.hypothesis_mem()
MemReqType, MemRespType = mk_mem_msg(obw, abw, 64)
s.run_test(msgs, mem, CacheReqType, CacheRespType, MemReqType,
MemRespType, 2, 64)
def main():
opts = parse_cmdline()
CacheReqType, CacheRespType = mk_mem_msg(opts.obw, opts.abw, opts.dbw)
MemReqType, MemRespType = mk_mem_msg(opts.obw, opts.abw, opts.clw)
# Instantiate the cache
dut = BlockingCacheRTL(CacheReqType, CacheRespType, MemReqType, \
MemRespType, opts.size, opts.asso)
success = False
dut.verilog_translate = True
# dut.config_verilog_translate = TranslationConfigs(
# explicit_module_name = 'BlockingCache_{}_{}_{}_{}_{}'.format(opts.size,
# opts.clw, opts.abw, opts.dbw, opts.asso),
# )
try:
dut.elaborate()
dut.apply(TranslationPass())
success = True
finally:
if success:
# path = os.path.join(os.getcwd(), f"{dut.translated_top_module_name}.sv")
print("\nTranslation finished successfully!")
# print(f"You can find the generated SystemVerilog file at {path}.")
else:
print("\nTranslation failed!")
def test_2way_hyp2(s,
dump_vcd,
test_verilog,
stall_prob=0,
latency=1,
src_delay=0,
sink_delay=0):
msgs = [
req('wr', 0x00, 0, 0, 0),
resp('wr', 0x00, 0, 0, 0),
req('rd', 0x01, 0x10, 0, 0),
resp('rd', 0x01, 0, 0, 3),
req('rd', 0x02, 0x10, 0, 0),
resp('rd', 0x02, 1, 0, 3),
req('rd', 0x03, 0x20, 0, 0),
resp('rd', 0x03, 0, 0, 4),
req('rd', 0x04, 0, 0, 0),
resp('rd', 0x04, 0, 0, 0),
]
mem = s.hypothesis_mem()
MemReqType, MemRespType = mk_mem_msg(obw, abw, 64)
s.run_test(msgs, mem, CacheReqType, CacheRespType, MemReqType, MemRespType, 2, 32, \
stall_prob, latency, src_delay, sink_delay)
def test_hypo_lat1(s, dump_vcd, test_verilog):
msgs = [
# type opq addr len data type opq test len data
req('rd', 0, 0x00000000, 0, 0),
resp('rd', 0x0, 0, 0, 0xa0b0c0d0),
req('rd', 1, 0x00000000, 0, 0),
resp('rd', 0x1, 1, 0, 0xa0b0c0d0),
]
mem = s.hypo_mem()
MemReqType, MemRespType = mk_mem_msg(obw, abw, 64)
s.run_test(msgs,
mem,
CacheReqType,
CacheRespType,
MemReqType,
MemRespType,
1,
128,
0,
1,
0,
1,
dump_vcd=dump_vcd,
test_verilog=test_verilog)
#=========================================================================
import pytest
import random
from pymtl3 import *
from pymtl3.stdlib.test.test_utils import mk_test_case_table
from pymtl3.stdlib.ifcs.SendRecvIfc import RecvCL2SendRTL, RecvIfcRTL, RecvRTL2SendCL, SendIfcRTL
from pymtl3.stdlib.test.test_srcs import TestSrcCL, TestSrcRTL
from pymtl3.stdlib.test.test_sinks import TestSinkCL, TestSinkRTL
from pymtl3.stdlib.test import run_sim
from pymtl3.stdlib.ifcs.MemMsg import MemMsgType, mk_mem_msg
from sram.SramPRTL import SramPRTL
from pymtl3.stdlib.rtl.registers import RegRst
MemReqMsg4B, MemRespMsg4B = mk_mem_msg(8, 10, 32)
class memWrapper(Component):
def construct(s, abw, nbl):
idw = clog2(nbl) # index width; clog2(512) = 9
twb_b = int(abw + 7) // 8 # Tag array write byte bitwidth
ab = mk_bits(abw)
ix = mk_bits(idw)
s.sramreq = RecvIfcRTL(MemReqMsg4B)
s.sramresp = SendIfcRTL(MemRespMsg4B)
s.sram_val = Wire(b1)
s.sram_type = Wire(b1)
s.sram_idx = Wire(ix)
Author : Xiaoyu Yan, Eric Tang
Date : 16 November 2019
"""
import pytest
import struct
import random
from pymtl3.stdlib.test.test_utils import mk_test_case_table
from pymtl3.stdlib.ifcs.MemMsg import MemMsgType, mk_mem_msg
obw = 8 # Short name for opaque bitwidth
abw = 32 # Short name for addr bitwidth
dbw = 32 # Short name for data bitwidth
clw = 128
CacheReqType, CacheRespType = mk_mem_msg(obw, abw, dbw)
MemReqType, MemRespType = mk_mem_msg(obw, abw, clw)
#-------------------------------------------------------------------------
# make messages
#-------------------------------------------------------------------------
def req(type_, opaque, addr, len, data):
if type_ == 'rd': type_ = MemMsgType.READ
elif type_ == 'wr': type_ = MemMsgType.WRITE
elif type_ == 'in': type_ = MemMsgType.WRITE_INIT
return CacheReqType(type_, opaque, addr, len, data)
def resp(type_, opaque, test, len, data):