def init(pru_bin): pypruss.modprobe(1024) ddr_addr = pypruss.ddr_addr() ddr_size = pypruss.ddr_size() print "DDR memory address is 0x%x and the size is 0x%x"%(ddr_addr, ddr_size) fifo = Fifo(ddr_addr, ddr_size) pypruss.init() pypruss.open(0) pypruss.pruintc_init() pypruss.pru_write_memory(0,0,[ddr_addr]) pypruss.exec_program(0, pru_bin) return fifo
def __init__(self, stopped, socket, ddr_mem):
super(PRUReadThread, self).__init__()
self.stopped = stopped
ddr_addr = 0x4a302000
ddr_size = pypruss.ddr_size()
ddr_offset = ddr_addr - 0x10000000
ddr_filelen = ddr_size + 0x10000000
ddr_start = 0x10000000
ddr_end = 0x10000000 + ddr_size
self.messages_base = ddr_start + 8
self.messages_ptr = self.messages_base
self.calls = 0
self.socket = socket
self.ddr_mem = ddr_mem
def __init__(self):
pru_hz = 200*1000*1000 # The PRU has a speed of 200 MHz
self.s_pr_inst = 1.0/pru_hz # I take it every instruction is a single cycle instruction
self.s_pr_inst_2 = 2.0*(1.0/pru_hz) # I take it every instruction is a single cycle instruction
self.inst_pr_loop = 16 # This is the minimum number of instructions needed to step.
self.inst_pr_delay = 2 # Every loop adds two instructions: i-- and i != 0
self.sec_to_inst_dev = (self.s_pr_inst*2)
self.pru_data = [] # This holds all data for one move (x,y,z,e1,e2)
self.ddr_used = Queue.Queue(30) # List of data lengths currently in DDR for execution
self.ddr_reserved = 0
self.ddr_mem_used = 0
self.clear_events = []
self.ddr_lock = Lock()
self.debug = 0
self.i = 0
pypruss.modprobe(0x40000) # This only has to be called once pr boot
self.ddr_addr = pypruss.ddr_addr()
self.ddr_size = pypruss.ddr_size()
print "The DDR memory reserved for the PRU is "+hex(self.ddr_size)+" and has addr "+hex(self.ddr_addr)
ddr_offset = self.ddr_addr-0x10000000 # The Python mmap function cannot accept unsigned longs.
ddr_filelen = self.ddr_size+0x10000000
self.DDR_START = 0x10000000
self.DDR_END = 0x10000000+self.ddr_size
self.ddr_start = self.DDR_START
self.ddr_nr_events = self.ddr_addr+self.ddr_size-4
with open("/dev/mem", "r+b") as f: # Open the memory device
self.ddr_mem = mmap.mmap(f.fileno(), ddr_filelen, offset=ddr_offset) # mmap the right area
self.ddr_mem[self.ddr_start:self.ddr_start+4] = struct.pack('L', 0) # Add a zero to the first reg to make it wait
pypruss.init() # Init the PRU
pypruss.open(0) # Open PRU event 0 which is PRU0_ARM_INTERRUPT
pypruss.pruintc_init() # Init the interrupt controller
pypruss.pru_write_memory(0, 0, [self.ddr_addr, self.ddr_nr_events]) # Put the ddr address in the first region
pypruss.exec_program(0, "../firmware/firmware_pru_0.bin") # Load firmware "ddr_write.bin" on PRU 0
self.t = Thread(target=self._wait_for_events) # Make the thread
self.running = True
self.t.start()
logging.debug("PRU initialized")
def init(pru_bin):
pypruss.modprobe(1024)
ddr_addr = pypruss.ddr_addr()
ddr_size = pypruss.ddr_size()
print "DDR memory address is 0x%x and the size is 0x%x"%(ddr_addr, ddr_size)
fifo = Fifo(ddr_addr, ddr_size)
pypruss.init()
pypruss.open(0)
pypruss.pruintc_init()
pru_init = [ddr_addr, len(axes)]
for step_addr, step_pin, dir_addr, dir_pin in axes:
pru_init += [step_addr+0x194, 1 << step_pin,
dir_addr+0x194, 1 << dir_pin,
0, 0]
pypruss.pru_write_memory(0,0,pru_init)
pypruss.exec_program(0, pru_bin)
return fifo
''' ddr_write.py - Finds the DDR address and size, passes that info to the PRU0
data memory, executes a program and reads back data from the first and last banks'''
import pypruss
import mmap
import struct
pypruss.modprobe()
ddr_addr = pypruss.ddr_addr()
ddr_size = pypruss.ddr_size()
print "DDR memory address is 0x%x and the size is 0x%x"%(ddr_addr, ddr_size)
ddr_offset = ddr_addr-0x10000000
ddr_filelen = ddr_size+0x10000000
ddr_start = 0x10000000
ddr_end = 0x10000000+ddr_size
pypruss.init() # Init the PRU
pypruss.open(0) # Open PRU event 0 which is PRU0_ARM_INTERRUPT
pypruss.pruintc_init() # Init the interrupt controller
pypruss.pru_write_memory(0, 0, [ddr_addr, ddr_addr+ddr_size-4]) # Put the ddr address in the first region
pypruss.exec_program(0, "./ddr_write.bin") # Load firmware "ddr_write.bin" on PRU 0
pypruss.wait_for_event(0) # Wait for event 0 which is connected to PRU0_ARM_INTERRUPT
pypruss.clear_event(0) # Clear the event
pypruss.exit() # Exit PRU
with open("/dev/mem", "r+b") as f: # Open the physical memory device
ddr_mem = mmap.mmap(f.fileno(), ddr_filelen, offset=ddr_offset) # mmap the right area
from __future__ import print_function
import pypruss
print("Running modprobe")
pypruss.modprobe(1000)
print("modprobe ok")
pypruss.init()
print("init ok")
pypruss.open(0)
print("open ok")
pypruss.pruintc_init()
print("intc ok")
print("ddr addr is " + hex(pypruss.ddr_addr()))
print("ddr size is " + hex(pypruss.ddr_size()))
pypruss.exit()
print("exit ok")
pypruss.modunprobe()
print("modunprobe ok")
import pypruss # available only in python 2
import select
import signal
import socket
import struct
import sys
import threading
import time
TARGET_PRU_FW = 'j17084truckduck.bin'
TARGET_PRU_NO = 1
UDP_PORTS = (6969, 6970)
DDR_START = 0x10000000 # 256MiB
DDR_VADDR = 0x4a300000
DDR_SIZE = pypruss.ddr_size()
DDR_END = DDR_START + DDR_SIZE
if TARGET_PRU_NO == 0:
TARGET_PRU_INTERRUPT = pypruss.PRU0_ARM_INTERRUPT
TARGET_PRU_PRE_SIZE = 0
else:
TARGET_PRU_INTERRUPT = pypruss.PRU1_ARM_INTERRUPT
TARGET_PRU_PRE_SIZE = 8192
SHARED_ADDR = DDR_VADDR + TARGET_PRU_PRE_SIZE
SHARED_OFFSET = SHARED_ADDR - DDR_START
SHARED_FILELEN = DDR_SIZE + DDR_START
PAYLOAD_LEN = 255 # must match the same in j17084truckduck.c
FRAME_SIZE = 256 # must match the same in j17084truckduck.c
''' ddr_write.py - Finds the DDR address and size, passes that info to the PRU0
data memory, executes a program and reads back data from the first and last banks'''
import pypruss
import mmap
import struct
pypruss.modprobe(1000)
ddr_addr = pypruss.ddr_addr()
ddr_size = pypruss.ddr_size()
print "DDR memory address is 0x%x and the size is 0x%x" % (ddr_addr, ddr_size)
ddr_offset = ddr_addr - 0x10000000
ddr_filelen = ddr_size + 0x10000000
ddr_start = 0x10000000
ddr_end = 0x10000000 + ddr_size
pypruss.init() # Init the PRU
pypruss.open(0) # Open PRU event 0 which is PRU0_ARM_INTERRUPT
pypruss.pruintc_init() # Init the interrupt controller
pypruss.pru_write_memory(0, 0, [ddr_addr, ddr_addr + ddr_size - 4
]) # Put the ddr address in the first region
pypruss.exec_program(
0, "./ddr_write.bin") # Load firmware "ddr_write.bin" on PRU 0
pypruss.wait_for_event(
0) # Wait for event 0 which is connected to PRU0_ARM_INTERRUPT
pypruss.clear_event(0) # Clear the event
pypruss.exit() # Exit PRU
with open("/dev/mem", "r+b") as f: # Open the physical memory device
def __init__(self, sr=0.0, smp_len=0):
""" Configures several BBB pins as necessary to hold the ADC in an idle state
Args:
cr: Conversion Rate (float)
smp_len: Sample Length (integer)
Parameters (in order of initialization):
self.DBus
self.WR
self._RD
self._CONVST
self._CS
self."ddr stuff"
self.n_channels
self.conversion_rate
self.deadband_ms
self.arm_status
self.seq_desc
self.ch
self.delay
self.digital_gain
self.threshold
self.corrected_threshold
self.cr_specd
self.modified
self.sample_rate
self.dac_voltage
self.LSB
self.TOF
self.TRG_CH
self.digital_gain
"""
# Loads the BBB cape overlays that allow control of the PRUSS
# and it's IO via pypruss. Note: pypruss will not work correctly
# until this system level command is ran. Do not try to use the
# pypruss library before running this command.
boot.load()
# GPIO Stuff
self.DBus = Port(DB_pin_table)
self.DBus.set_port_dir("in")
self.WR = Port(WR_pin)
self.WR.set_port_dir("out")
self.WR.write_to_port(1)
self._RD = Port(RD_pin)
self._RD.set_port_dir("out")
self._RD.write_to_port(1)
self._CONVST = Port(CONVST_pin)
self._CONVST.set_port_dir("out")
self._CONVST.write_to_port(1)
self._CS = Port(CS_pin)
self._CS.set_port_dir("out")
self._CS.write_to_port(0)
# PRUSS Stuff
self.ddr = {}
self.ddr['addr'] = pypruss.ddr_addr()
self.ddr['size'] = pypruss.ddr_size()
self.ddr['start'] = 0x10000000
self.ddr['filelen'] = self.ddr['size'] + 0x10000000
self.ddr['offset'] = self.ddr['addr'] - 0x10000000
self.ddr['end'] = 0x10000000 + self.ddr['size']
msg = ("ADS7865: Allowing one 32bit memory block per sample, it is "
"possible to collect {samp:.1f}K Samples in a single burst. These "
"sample points are stored in DDRAM, which is found at the "
"address range starting at {addr}")
logging.info(msg.format(
samp=self.ddr['size'] / 1000.0,
addr=str(hex(self.ddr['addr'])))
)
self.sampling_rate = sr
self.deadband_ms = 0
self.sample_length = int(smp_len)
self.arm_status = "unknown"
self.seq_desc = "unknown"
self.ch = ['unknown'] * 4
self.delay = [-99] * 4
self.digital_gain = 1
self.update_threshold(DEFAULT_THRESHOLD)
self.sr_specd = 0 # parameter for keeping the up with the last spec
self.modified = True
self.sample_rate = None
self.dac_voltage = DEFAULT_DAC_VOLTAGE
self.lsb = self.dac_voltage / (2**(WORD_SIZE - 1)) # Volts
# Loads overlays: For that will be later needed for
# muxing pins from GPIO to pruout/pruin types and vice versa.
self.sw_reset()
# Any other variables that will later be relevent
self.TOF = None
self.TRG_CH = None
self.y = None