Esempio n. 1
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    def test_select_with_5_wires(self):
        val_width = 5
        sels, sel_vals = utils.make_inputs_and_values(5, exact_bitwidth=1, test_vals=50)
        mux_ins, vals = utils.make_inputs_and_values(5, exact_bitwidth=val_width, test_vals=50)

        out = pyrtl.Output(val_width, "out")
        out <<= muxes.prioritized_mux(sels, mux_ins)
        actual = utils.sim_and_ret_out(out, sels + mux_ins, sel_vals + vals)
        expected = [pri_mux_actual(sel, val) for sel, val in zip(zip(*sel_vals), zip(*vals))]
        self.assertEqual(actual, expected)
Esempio n. 2
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    def adder_t_base(self, adder_func, **kwargs):
        wires, vals = utils.make_inputs_and_values(dist=utils.inverse_power_dist, **kwargs)
        outwire = pyrtl.Output(name="test")
        outwire <<= adder_func(*wires)

        out_vals = utils.sim_and_ret_out(outwire, wires, vals)
        true_result = [sum(cycle_vals) for cycle_vals in zip(*vals)]
        self.assertEqual(out_vals, true_result)
Esempio n. 3
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    def test_fast_group_adder_1(self):
        wires, vals = utils.make_inputs_and_values(max_bitwidth=12, num_wires=7,
                                                   dist=utils.inverse_power_dist)
        outwire = pyrtl.Output(name="test")
        outwire <<= adders.fast_group_adder(wires)

        out_vals = utils.sim_and_ret_out(outwire, wires, vals)
        true_result = [sum(cycle_vals) for cycle_vals in zip(*vals)]
        self.assertEqual(out_vals, true_result)
Esempio n. 4
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    def test_fast_group_adder_1(self):
        wires, vals = utils.make_inputs_and_values(
            max_bitwidth=12, num_wires=7, dist=utils.inverse_power_dist)
        outwire = pyrtl.Output(name="test")
        outwire <<= adders.fast_group_adder(wires)

        out_vals = utils.sim_and_ret_out(outwire, wires, vals)
        true_result = [sum(cycle_vals) for cycle_vals in zip(*vals)]
        self.assertEqual(out_vals, true_result)
Esempio n. 5
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    def adder_t_base(self, adder_func, **kwargs):
        wires, vals = utils.make_inputs_and_values(
            dist=utils.inverse_power_dist, **kwargs)
        outwire = pyrtl.Output(name="test")
        outwire <<= adder_func(*wires)

        out_vals = utils.sim_and_ret_out(outwire, wires, vals)
        true_result = [sum(cycle_vals) for cycle_vals in zip(*vals)]
        self.assertEqual(out_vals, true_result)
Esempio n. 6
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    def test_xor(self):
        wires, vals = utils.make_inputs_and_values(7, exact_bitwidth=8, dist=utils.uniform_dist)
        outwire = pyrtl.Output(name="test")

        import operator
        from six.moves import reduce
        outwire <<= pyrtl.tree_reduce(operator.xor, wires)

        out_vals = utils.sim_and_ret_out(outwire, wires, vals)
        true_result = [reduce(operator.xor, v) for v in zip(*vals)]
        self.assertEqual(out_vals, true_result)
Esempio n. 7
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    def test_partition_sim(self):
        pyrtl.reset_working_block()
        wires, vals = utils.make_inputs_and_values(exact_bitwidth=32, num_wires=1)
        out_wires = [pyrtl.Output(8, 'o' + str(i)) for i in range(4)]
        partitioned_w = libutils.partition_wire(wires[0], 8)
        for p_wire, o_wire in zip(partitioned_w, out_wires):
            o_wire <<= p_wire

        out_vals = utils.sim_and_ret_outws(wires, vals)
        partitioned_vals = [[(val >> i) & 0xff for i in (0, 8, 16, 24)] for val in vals[0]]
        true_vals = tuple(zip(*partitioned_vals))
        for index, wire in enumerate(out_wires):
            self.assertEqual(tuple(out_vals[wire.name]), true_vals[index])
    def test_partition_sim(self):
        pyrtl.reset_working_block()
        wires, vals = utils.make_inputs_and_values(exact_bitwidth=32, num_wires=1)
        out_wires = [pyrtl.Output(8, 'o' + str(i)) for i in range(4)]
        partitioned_w = libutils.partition_wire(wires[0], 8)
        for p_wire, o_wire in zip(partitioned_w, out_wires):
            o_wire <<= p_wire

        out_vals = utils.sim_and_ret_outws(wires, vals)
        partitioned_vals = [[(val >> i) & 0xff for i in (0, 8, 16, 24)] for val in vals[0]]
        true_vals = tuple(zip(*partitioned_vals))
        for index, wire in enumerate(out_wires):
            self.assertEqual(tuple(out_vals[wire]), true_vals[index])
Esempio n. 9
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    def test_fma_1(self):
        wires, vals = utils.make_inputs_and_values(exact_bitwidth=10, num_wires=3,
                                                   dist=utils.inverse_power_dist)
        test_w = multipliers.fused_multiply_adder(wires[0], wires[1], wires[2], False,
                                                  reducer=adders.dada_reducer,
                                                  adder_func=adders.ripple_add)
        self.assertEqual(len(test_w), 20)
        outwire = pyrtl.Output(21, "test")
        outwire <<= test_w

        out_vals = utils.sim_and_ret_out(outwire, wires, vals)
        true_result = [vals[0][cycle] * vals[1][cycle] + vals[2][cycle]
                       for cycle in range(len(vals[0]))]
        self.assertEqual(out_vals, true_result)
Esempio n. 10
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    def test_gen_fma_1(self):
        wires, vals = utils.make_inputs_and_values(max_bitwidth=8, num_wires=8,
                                                   dist=utils.inverse_power_dist)
        # mixing tuples and lists solely for readability purposes
        mult_pairs = [(wires[0], wires[1]), (wires[2], wires[3]), (wires[4], wires[5])]
        add_wires = (wires[6], wires[7])

        outwire = pyrtl.Output(name="test")
        outwire <<= multipliers.generalized_fma(mult_pairs, add_wires, signed=False)

        out_vals = utils.sim_and_ret_out(outwire, wires, vals)
        true_result = [vals[0][cycle] * vals[1][cycle] + vals[2][cycle] * vals[3][cycle] +
                       vals[4][cycle] * vals[5][cycle] + vals[6][cycle] + vals[7][cycle]
                       for cycle in range(len(vals[0]))]
        self.assertEqual(out_vals, true_result)
Esempio n. 11
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    def test_fma_1(self):
        wires, vals = utils.make_inputs_and_values(
            exact_bitwidth=10, num_wires=3, dist=utils.inverse_power_dist)
        test_w = multipliers.fused_multiply_adder(wires[0],
                                                  wires[1],
                                                  wires[2],
                                                  False,
                                                  reducer=adders.dada_reducer,
                                                  adder_func=adders.ripple_add)
        self.assertEqual(len(test_w), 20)
        outwire = pyrtl.Output(21, "test")
        outwire <<= test_w

        out_vals = utils.sim_and_ret_out(outwire, wires, vals)
        true_result = [
            vals[0][cycle] * vals[1][cycle] + vals[2][cycle]
            for cycle in range(len(vals[0]))
        ]
        self.assertEqual(out_vals, true_result)
Esempio n. 12
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    def test_gen_fma_1(self):
        wires, vals = utils.make_inputs_and_values(
            max_bitwidth=8, num_wires=8, dist=utils.inverse_power_dist)
        # mixing tuples and lists solely for readability purposes
        mult_pairs = [(wires[0], wires[1]), (wires[2], wires[3]),
                      (wires[4], wires[5])]
        add_wires = (wires[6], wires[7])

        outwire = pyrtl.Output(name="test")
        outwire <<= multipliers.generalized_fma(mult_pairs,
                                                add_wires,
                                                signed=False)

        out_vals = utils.sim_and_ret_out(outwire, wires, vals)
        true_result = [
            vals[0][cycle] * vals[1][cycle] + vals[2][cycle] * vals[3][cycle] +
            vals[4][cycle] * vals[5][cycle] + vals[6][cycle] + vals[7][cycle]
            for cycle in range(len(vals[0]))
        ]
        self.assertEqual(out_vals, true_result)
Esempio n. 13
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 def test_list_of_long_wires(self):
     in_wires, vals = utils.make_inputs_and_values(4, exact_bitwidth=13)
     out = pyrtl.Output(name='o')
     out <<= pyrtl.corecircuits.xor_all_bits(in_wires)
     expected = [v1 ^ v2 ^ v3 ^ v4 for v1, v2, v3, v4 in zip(*vals)]
     self.assertEqual(expected, utils.sim_and_ret_out(out, in_wires, vals))
Esempio n. 14
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 def test_list_of_long_wires(self):
     in_wires, vals = utils.make_inputs_and_values(4, exact_bitwidth=13)
     out = pyrtl.Output(name='o')
     out <<= pyrtl.corecircuits.xor_all_bits(in_wires)
     expected = [v1 ^ v2 ^ v3 ^ v4 for v1, v2, v3, v4 in zip(*vals)]
     self.assertEqual(expected, utils.sim_and_ret_out(out, in_wires, vals))