def gen_lat(path):
clk = vast.Ioport(vast.Input('en'))
q = vast.Ioport(vast.Output('Q'))
d = vast.Ioport(vast.Input('D'))
r = vast.Ioport(vast.Input('rst'))
ports = vast.Portlist([clk, q, d, r])
q_reg = vast.Identifier('reg Q = 0;')
sens = []
sens.append(vast.Sens(vast.Identifier('en'), type='level'))
sens.append(vast.Sens(vast.Identifier('rst'), type='level'))
sens.append(vast.Sens(vast.Identifier('D'), type='level'))
senslist = vast.SensList(sens)
assign_q = vast.NonblockingSubstitution(vast.Lvalue(vast.Identifier('Q')),
vast.Rvalue(vast.Identifier('D')))
blocks = []
blocks.append(
vast.IfStatement(
vast.Identifier('rst'), vast.Identifier('Q <= 0;'),
vast.IfStatement(vast.Identifier('en'), assign_q, None), None))
statement = vast.Block(blocks)
always = vast.Always(senslist, statement)
items = []
items.append(q_reg)
items.append(always)
ast = vast.ModuleDef("lat", None, ports, items)
write_verilog(ast, 'lat.v', path)
def visit_GenerateIf(self, node):
genif_visitor = VerilogBlockingVisitor()
cond = genif_visitor.visit(node.cond)
true_items = self._visit_Generate(node)
true_block = vast.Block(true_items, scope=node.true_scope)
false_items = self._visit_Generate(node.Else)
false_block = (vast.Block(false_items, scope=node.Else.false_scope)
if false_items else None)
_if = vast.IfStatement(cond, true_block, false_block)
return vast.GenerateStatement(tuple([_if]))
def test():
datawid = vast.Parameter( 'DATAWID', vast.Rvalue(vast.IntConst('32')) )
params = vast.Paramlist( [datawid] )
clk = vast.Ioport( vast.Input('CLK') )
rst = vast.Ioport( vast.Input('RST') )
width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
led = vast.Ioport( vast.Output('led', width=width) )
ports = vast.Portlist( [clk, rst, led] )
width = vast.Width( vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), vast.IntConst('0') )
count = vast.Reg('count', width=width)
assign = vast.Assign(
vast.Lvalue(vast.Identifier('led')),
vast.Rvalue(
vast.Partselect(
vast.Identifier('count'), # count
vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1:
vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8]
sens = vast.Sens(vast.Identifier('CLK'), type='posedge')
senslist = vast.SensList([ sens ])
assign_count_true = vast.NonblockingSubstitution(
vast.Lvalue(vast.Identifier('count')),
vast.Rvalue(vast.IntConst('0')))
if0_true = vast.Block([ assign_count_true ])
# (count + 1) * 2
count_plus_1 = vast.Plus(vast.Identifier('count'), vast.IntConst('1'))
cp1_times_2 = vast.Times(count_plus_1, vast.IntConst('2'))
cp1t2_plus_1 = vast.Plus(cp1_times_2, vast.IntConst('1'))
assign_count_false = vast.NonblockingSubstitution(
vast.Lvalue(vast.Identifier('count')),
vast.Rvalue(cp1t2_plus_1))
if0_false = vast.Block([ assign_count_false ])
if0 = vast.IfStatement(vast.Identifier('RST'), if0_true, if0_false)
statement = vast.Block([ if0 ])
always = vast.Always(senslist, statement)
items = []
items.append(count)
items.append(assign)
items.append(always)
ast = vast.ModuleDef("top", params, ports, items)
codegen = ASTCodeGenerator()
rslt = codegen.visit(ast)
print(rslt)
assert(expected == rslt)
def visit_If(self, node):
cond = self.visit(node.condition)
true_statement = self.visit(node.true_statement)
false_statement = (self.visit(node.false_statement)
if node.false_statement is not None else None)
# remove a redundant begin-end, if the true_statement is not for reset
cond_str = str(cond).lower()
if ((not cond_str.count('rst') and not cond_str.count('reset'))
and isinstance(false_statement, vast.Block)
and len(false_statement.statements) == 1 and isinstance(
false_statement.statements[0], vast.IfStatement)):
false_statement = false_statement.statements[0]
return vast.IfStatement(cond, true_statement, false_statement)