def test_measure_with_final_permutation(p):
problem = nx.complete_graph(n=5)
problem = random_plus_minus_1_weights(problem)
qubits = cirq.LineQubit.range(5)
c1 = cirq.Circuit(cirq.H.on_each(qubits), [[
ProblemUnitary(problem, gamma=np.random.random()).on(*qubits),
DriverUnitary(5, beta=np.random.random()).on(*qubits)
] for _ in range(p)])
c2 = compile_problem_unitary_to_swap_network(c1)
c3 = compile_swap_network_to_zzswap(c2)
c4 = compile_driver_unitary_to_rx(c3)
c5 = compile_to_syc(c4)
validate_well_structured(c5, allow_terminal_permutations=True)
c6, final_qubits = measure_with_final_permutation(c5, qubits)
validate_well_structured(c6, allow_terminal_permutations=False)
if p % 2 == 1:
assert final_qubits == qubits[::-1]
else:
assert final_qubits == qubits
permutation = []
for q in qubits:
permutation.append(final_qubits.index(q))
c1_prime = (c1 +
QuirkQubitPermutationGate('', '', permutation).on(*qubits) +
cirq.measure(*qubits, key='z'))
cirq.testing.assert_circuits_with_terminal_measurements_are_equivalent(
c1_prime, c6, atol=1e-5)
def test_compile_to_syc(p):
problem = nx.complete_graph(n=5)
problem = random_plus_minus_1_weights(problem)
qubits = cirq.LineQubit.range(5)
c1 = cirq.Circuit(
cirq.H.on_each(qubits),
[
[
ProblemUnitary(problem, gamma=np.random.random()).on(*qubits),
DriverUnitary(5, beta=np.random.random()).on(*qubits)
]
for _ in range(p)
]
)
c2 = compile_problem_unitary_to_swap_network(c1)
c3 = compile_swap_network_to_zzswap(c2)
c4 = compile_driver_unitary_to_rx(c3)
c5 = compile_to_syc(c4)
validate_well_structured(c5, allow_terminal_permutations=True)
np.testing.assert_allclose(c1.unitary(), c2.unitary())
np.testing.assert_allclose(c1.unitary(), c3.unitary())
np.testing.assert_allclose(c1.unitary(), c4.unitary())
# Single qubit throws out global phase
cirq.testing.assert_allclose_up_to_global_phase(
c1.unitary(), c5.unitary(), atol=1e-8)
def get_compiled_sk_model_circuit(
problem: SKProblem,
qubits: List[cirq.Qid],
gammas: Sequence[float],
betas: Sequence[float],
*,
non_negligible=True
) -> Tuple[cirq.Circuit, List[cirq.Qid]]:
"""Get a fully-compiled SK model circuit.
Args:
problem: A SKProblem
qubits: The qubits to use in construction of the circuit.
gammas: Gamma angles to use as parameters for problem unitaries
betas: Beta angles to use as parameters for driver unitaries
non_negligible: Whether to compile out negligible gates. This will
preserve the quality that the returned circuit has homogeneous
gate types in each moment but may make it so the predictable
pattern of PhX, (SYC, PhX)*n, PhX may be disrupted. Set this
argument to `False` if doing echo experiments.
Returns:
circuit: The final routed, gateset-targeted, and placed circuit with
measurements.
final_qubits: The qubits in their final logical order.
"""
circuit = get_routed_sk_model_circuit(problem.graph, qubits, gammas, betas)
circuit = compile_to_syc(circuit)
mcircuit, final_qubits = measure_with_final_permutation(circuit, qubits)
mcircuit = compile_out_virtual_z(mcircuit)
if non_negligible:
mcircuit = compile_to_non_negligible(mcircuit)
validate_well_structured(mcircuit)
return mcircuit, final_qubits
def test_compile_out_virtual_z():
qubits = cirq.LineQubit.range(2)
circuit = cirq.Circuit(ZZSwap(zz_exponent=0.123).on(*qubits))
c1 = compile_to_syc(circuit)
assert len(c1) == 3 * 3 + 2
c2 = compile_out_virtual_z(c1)
assert c1 != c2
assert len(c2) == 3 * 2 + 2
def test_compile_to_non_negligible():
qubits = cirq.LineQubit.range(2)
circuit = cirq.Circuit(ZZSwap(zz_exponent=0.123).on(*qubits))
c1 = compile_to_syc(circuit)
validate_well_structured(c1)
assert len(c1) == 3 * 3 + 2
c2 = compile_to_non_negligible(c1)
assert c1 != c2
# KAK instability (https://github.com/quantumlib/Cirq/issues/1647)
# means the first layer of PhX gets removed on mpharrigan's machine
# but not in docker / in CI.
assert len(c2) in [9, 10]
def get_compiled_hardware_grid_circuit(
problem: HardwareGridProblem,
qubits: List[cirq.Qid],
gammas: Sequence[float],
betas: Sequence[float],
non_negligible=True) \
-> Tuple[cirq.Circuit, List[cirq.Qid]]:
"""Get a fully-compiled grid model circuit.
Args:
problem: A HardwareGridProblem
qubits: The qubits to use in construction of the circuit.
gammas: Gamma angles to use as parameters for problem unitaries
betas: Beta angles to use as parameters for driver unitaries
non_negligible: Whether to compile out negligible gates. This will
preserve the quality that the returned circuit has homogeneous
gate types in each moment but may make it so the predictable
pattern of PhX, (SYC, PhX)*n, PhX may be disrupted. Set this
argument to `False` if doing echo experiments.
Returns:
circuit: The final routed, gateset-targeted, and placed circuit with
measurements.
final_qubits: The qubits in their final logical order. This is for
consistency with other problem types. This will be a copy of
`qubits`.
"""
circuit = get_routed_hardware_grid_circuit(
problem_graph=problem.graph,
qubits=qubits,
coordinates=problem.coordinates,
gammas=gammas,
betas=betas)
circuit = compile_to_syc(circuit)
mcircuit = circuit + cirq.measure(*qubits, key='z')
mcircuit = compile_out_virtual_z(mcircuit)
if non_negligible:
mcircuit = compile_to_non_negligible(mcircuit)
validate_well_structured(mcircuit)
final_qubits = qubits.copy()
return mcircuit, final_qubits
def test_get_moment_classes():
n = 5
problem = nx.complete_graph(n=n)
problem = random_plus_minus_1_weights(problem)
qubits = cirq.LineQubit.range(n)
p = 1
c1 = cirq.Circuit(cirq.H.on_each(qubits), [[
ProblemUnitary(problem, gamma=np.random.random()).on(*qubits),
DriverUnitary(5, beta=np.random.random()).on(*qubits)
] for _ in range(p)])
c2 = compile_problem_unitary_to_swap_network(c1)
c3 = compile_swap_network_to_zzswap(c2)
c4 = compile_driver_unitary_to_rx(c3)
c5 = compile_to_syc(c4)
mom_classes = get_moment_classes(c5)
should_be = [cirq.PhasedXPowGate, cirq.ZPowGate, cg.SycamoreGate
] * (n * p * 3)
should_be += [
cirq.PhasedXPowGate, cirq.ZPowGate, QuirkQubitPermutationGate
]
assert mom_classes == should_be
def test_structured():
qubits = cirq.LineQubit.range(2)
circuit = cirq.Circuit(ZZSwap(zz_exponent=0.123).on(*qubits))
circuit = compile_to_syc(circuit)
validate_well_structured(circuit)