def generate_top_ral(top: Dict[str, object], name_to_block: Dict[str, IpBlock],
dv_base_prefix: str, out_path: str):
# construct top ral block
regwidth = int(top['datawidth'])
assert regwidth % 8 == 0
addrsep = regwidth // 8
# Generate a map from instance name to the block that it instantiates,
# together with a map of interface addresses.
inst_to_block = {} # type: Dict[str, str]
if_addrs = {} # type: Dict[Tuple[str, Optional[str]], int],
attrs = {} # type: Dict[str, str]
for module in top['module']:
inst_name = module['name']
block_name = module['type']
block = name_to_block[block_name]
if "attr" in module:
if module["attr"] not in [
'templated', 'reggen_top', 'reggen_only'
]:
raise ValueError(
'Unsupported value for attr field of {}: {!r}'.format(
inst_name, module["attr"]))
attrs[inst_name] = module["attr"]
inst_to_block[inst_name] = block_name
for if_name in block.reg_blocks.keys():
if_addr = int(module["base_addrs"][if_name], 0)
if_addrs[(inst_name, if_name)] = if_addr
# Collect up the memories to add
mems = []
for item in list(top.get("memory", [])):
byte_write = ('byte_write' in item
and item["byte_write"].lower() == "true")
data_intg_passthru = ('data_intg_passthru' in item
and item["data_intg_passthru"].lower() == "true")
size_in_bytes = int(item['size'], 0)
num_regs = size_in_bytes // addrsep
swaccess = access.SWAccess('top-level memory',
item.get('swaccess', 'rw'))
mems.append(
window.Window(name=item['name'],
desc='(generated from top-level)',
unusual=False,
byte_write=byte_write,
data_intg_passthru=data_intg_passthru,
validbits=regwidth,
items=num_regs,
size_in_bytes=size_in_bytes,
offset=int(item["base_addr"], 0),
swaccess=swaccess))
chip = Top(regwidth, name_to_block, inst_to_block, if_addrs, mems, attrs)
# generate the top ral model with template
return gen_dv(chip, dv_base_prefix, str(out_path))
def generate_top_ral(top, ip_objs, dv_base_prefix, out_path):
# construct top ral block
top_block = gen_rtl.Block()
top_block.name = "chip"
top_block.base_addr = 0
top_block.width = int(top["datawidth"])
# add all the IPs into blocks
for ip_obj in ip_objs:
top_block.blocks.append(gen_rtl.json_to_reg(ip_obj))
assert top_block.width % 8 == 0
reg_width_in_bytes = top_block.width // 8
# add memories
for item in list(top.get("memory", [])):
byte_write = ('byte_write' in item
and item["byte_write"].lower() == "true")
size_in_bytes = int(item['size'], 0)
num_regs = size_in_bytes // reg_width_in_bytes
swaccess = access.SWAccess('top-level memory',
item.get('swaccess', 'rw'))
mem = window.Window(name=item['name'],
desc='(generated from top-level)',
unusual=False,
byte_write=byte_write,
validbits=top_block.width,
items=num_regs,
size_in_bytes=size_in_bytes,
offset=int(item["base_addr"], 0),
swaccess=swaccess)
top_block.wins.append(mem)
# get sub-block base addresses, instance names from top cfg
for block in top_block.blocks:
for module in top["module"]:
if block.name == module["type"]:
block.base_addr[module["name"]] = int(module["base_addr"], 0)
# sort by the base_addr of 1st instance of the block
top_block.blocks.sort(key=lambda block: next(iter(block.base_addr))[1])
top_block.wins.sort(key=lambda win: win.offset)
# generate the top ral model with template
gen_dv.gen_ral(top_block, dv_base_prefix, str(out_path))
def create_mem(item, addrsep, regwidth):
byte_write = ("byte_write" in item
and item["byte_write"].lower() == "true")
data_intg_passthru = ("data_intg_passthru" in item
and item["data_intg_passthru"].lower() == "true")
size_in_bytes = int(item["size"], 0)
num_regs = size_in_bytes // addrsep
swaccess = access.SWAccess("top-level memory", item.get("swaccess", "rw"))
return window.Window(name=item["name"],
desc="(generated from top-level)",
unusual=False,
byte_write=byte_write,
data_intg_passthru=data_intg_passthru,
validbits=regwidth,
items=num_regs,
size_in_bytes=size_in_bytes,
offset=int(item.get("base_addr", "0"), 0),
swaccess=swaccess)
def create_mem(item, addrsep, regwidth):
byte_write = ('byte_write' in item
and item["byte_write"].lower() == "true")
data_intg_passthru = ('data_intg_passthru' in item
and item["data_intg_passthru"].lower() == "true")
size_in_bytes = int(item['size'], 0)
num_regs = size_in_bytes // addrsep
swaccess = access.SWAccess('top-level memory', item.get('swaccess', 'rw'))
return window.Window(name=item['name'],
desc='(generated from top-level)',
unusual=False,
byte_write=byte_write,
data_intg_passthru=data_intg_passthru,
validbits=regwidth,
items=num_regs,
size_in_bytes=size_in_bytes,
offset=int(item.get('base_addr', '0'), 0),
swaccess=swaccess)
def generate_top_ral(top, ip_objs, dv_base_prefix, out_path):
# construct top ral block
regwidth = int(top['datawidth'])
assert regwidth % 8 == 0
addrsep = regwidth // 8
# Get sub-block base addresses and instance names from top cfg
sub_blocks = {} # type: Dict[int, Tuple[str, IpBlock]]
for block in ip_objs:
block_lname = block.name.lower()
for module in top["module"]:
if block_lname == module["type"]:
block_addr = int(module["base_addr"], 0)
assert block_addr not in sub_blocks
sub_blocks[block_addr] = (module["name"], block)
# Collect up the memories to add
mems = []
for item in list(top.get("memory", [])):
byte_write = ('byte_write' in item
and item["byte_write"].lower() == "true")
size_in_bytes = int(item['size'], 0)
num_regs = size_in_bytes // addrsep
swaccess = access.SWAccess('top-level memory',
item.get('swaccess', 'rw'))
mems.append(
window.Window(name=item['name'],
desc='(generated from top-level)',
unusual=False,
byte_write=byte_write,
validbits=regwidth,
items=num_regs,
size_in_bytes=size_in_bytes,
offset=int(item["base_addr"], 0),
swaccess=swaccess))
chip = Top(regwidth, sub_blocks, mems)
# generate the top ral model with template
gen_dv.gen_ral(chip, dv_base_prefix, str(out_path))
