def init_muxs(self):
"""
Register clock mux to the clock tree
"""
Mux(tree=self.tree,
name="RTCSEL",
mux_field=self.RCC.BDCR.RTCSEL,
parents={
0: None,
1: 'LSE',
2: 'LSI',
3: 'HSERTC'
})
# TODO add suppport of mux status
Mux(tree=self.tree,
name="SW",
mux_field=self.RCC.CFGR.SW,
parents={
0: 'HSI',
1: 'HSE',
2: 'PLLCLK',
3: None
})
Mux(tree=self.tree,
name="I2SSRC",
mux_field=self.RCC.CFGR.I2SSRC,
parents={
0: 'PLLI2S',
1: 'I2SCKIN'
})
def __init__(self, device):
super(BL123ClockTree, self).__init__(device)
device.tree = self
clk0 = device.CLOCK0
FixedClock(tree=self, name='OSC0',
freq=MHz(1), en_field=clk0.OSC0.EN)
FixedClock(tree=self, name='OSC1',
freq=MHz(8), en_field=clk0.OSC1.EN)
FixedClock(tree=self, name='OSC2',
freq=MHz(16), en_field=clk0.OSC2.EN)
Mux(tree=self, name='PLLSRC',
parents={0: 'OSC0', 1: 'OSC1', 2: 'OSC2'}, mux_field=clk0.PLL.SRC)
PLL(tree=self, name='PLL', parent='PLLSRC',
get_freq=pll_get_freq, en_field=clk0.PLL.EN)
Mux(tree=self, name='BUS0SRC', mux_field=clk0.BUS0.SRC,
parents={0: 'OSC0', 1: 'OSC1', 2: 'OSC2', 3: 'PLL'})
Divider(tree=self, name='BUS0DIV', parent='BUS0SRC',
div_field=clk0.BUS0.DIV, div_type=Divider.POWER_OF_TWO)
Divider(tree=self, name='BUS1DIV', parent='BUS0DIV',
div_field=clk0.BUS1.DIV, div_type=Divider.POWER_OF_TWO)
Gate(tree=self, name='UART0', parent='BUS0DIV',
en_field=clk0.UART0.EN)
Gate(tree=self, name='UART1', parent='BUS0DIV',
en_field=clk0.UART1.EN)
Gate(tree=self, name='GPIO0', parent='BUS1DIV',
en_field=clk0.GPIO0.EN)
Gate(tree=self, name='GPIO1', parent='BUS1DIV',
en_field=clk0.GPIO1.EN)
Gate(tree=self, name='GPIO2', parent='BUS1DIV',
en_field=clk0.GPIO2.EN)
Gate(tree=self, name='GPIO3', parent='BUS1DIV',
en_field=clk0.GPIO3.EN)
def test_get_parent(self):
parent = self.mux.get_parent()
self.assertEqual(parent.name, 'test3')
mux = Mux(name='mux',
tree=self.tree,
parents=self.mux_parents,
get_mux=ext_get_mux)
parent = mux.get_parent()
self.assertEqual(parent.name, 'test0')
def test_enabled(self):
mux = Mux(name='pll',
tree=self.tree,
parents={
0: 'test0',
3: None
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertFalse(mux.enabled())
self.dev.TEST1.TESTA.A3.write(0)
self.assertTrue(mux.enabled())
self.dev.TEST1.TESTA.A3.write(3)
def test_get_freq(self):
self.assertEqual(self.mux._get_freq(), 12345)
mux = Mux(name='pll',
tree=self.tree,
parents={
0: 'test0',
1: 'test1',
3: None
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertEqual(mux.get_freq(), 0)
def setUpClass(self):
super(TestMux, self).setUpClass()
self.mux_field = self.dev.TEST1.TESTA.A3
self.tree = ClockTree(self.dev)
FixedClock(name='test0', tree=self.tree, freq=1234)
FixedClock(name='test1', tree=self.tree, freq=123456)
FixedClock(name='test3', tree=self.tree, freq=12345)
self.mux_parents = {0: 'test0', 1: 'test1', 3: 'test3'}
self.mux = Mux(name='muxe',
tree=self.tree,
parents=self.mux_parents,
mux_field=self.mux_field)
def setUpClass(self):
super(TestClockTree, self).setUpClass()
FixedClock(name='osc1', tree=self.tree, freq=1234)
FixedClock(name='osc2', tree=self.tree, freq=2345)
FixedClock(name='osc3', tree=self.tree, freq=5432)
Mux(name='mux1',
tree=self.tree,
mux_field=self.dev.TEST1.TESTA.A3,
parents={
0: 'osc1',
1: 'osc2',
2: 'osc3',
3: 'osc3'
})
Divider(name='div1', tree=self.tree, div=2, parent='osc1')
Divider(name='div2', tree=self.tree, div=4, parent='mux1')
Gate(name='gate1',
tree=self.tree,
parent='div1',
en_field=self.dev.TEST1.TESTA.A1)
Gate(name='gate2',
tree=self.tree,
parent='div2',
en_field=self.dev.TEST1.TESTA.A2)
Divider(name='div3', tree=self.tree, div=2, parent='gate2')
def init_plls(self):
"""
Add PLL clocks to clock tree
In addition of PLL clocks, there are two internals clocks
also defined (e.g VCO clocks). They are internal to the PLL
but because they are derived for PLL output and because we have
apply a frequency constraint, they have been added as any clock.
"""
reg = self.RCC.PLLCFGR
Mux(tree=self.tree,
name='PLLSRC',
parents={
0: 'HSI',
1: 'HSE'
},
mux_field=reg.PLLSRC)
PLL(tree=self.tree,
name='PLLVCO',
parent='PLLSRC',
get_freq=get_vco_freq,
en_field=self.RCC.CR.PLLON,
min=MHz(100),
max=MHz(432))
PLL(tree=self.tree,
name='PLLCLK',
parent='PLLVCO',
get_freq=get_pll_freq)
PLL(tree=self.tree,
name='PLLUSBOTGFS',
parent='PLLVCO',
get_freq=get_usb_otg_fs_freq)
PLL(tree=self.tree,
name='PLLI2SVCO',
parent='PLLSRC',
get_freq=get_plli2s_vco_freq,
en_field=self.RCC.CR.PLLI2SON,
min=MHz(100),
max=MHz(432))
PLL(tree=self.tree,
name='PLLI2S',
parent='PLLI2SVCO',
get_freq=get_plli2s_freq)
def test_build(self):
mux = Mux()
self.assertFalse(mux.build())
mux = Mux(parents={0: 'parent1', 1: 'parent2'})
self.assertFalse(mux.build())
mux = Mux(parents={
0: 'parent1',
1: 'parent2'
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertFalse(mux.build())
mux = Mux(tree=self.tree,
parents={
0: 'test0',
1: 'test4'
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertFalse(mux.build())
mux = Mux(tree=self.tree,
parents={
0: 'test0',
1: 'test1'
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertTrue(mux.build())
mux = Mux(tree=self.tree,
parents={
0: 'test0',
1: 'test1',
2: None
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertTrue(mux.build())
class TestMux(ClockTestCase):
@classmethod
def setUpClass(self):
super(TestMux, self).setUpClass()
self.mux_field = self.dev.TEST1.TESTA.A3
self.tree = ClockTree(self.dev)
FixedClock(name='test0', tree=self.tree, freq=1234)
FixedClock(name='test1', tree=self.tree, freq=123456)
FixedClock(name='test3', tree=self.tree, freq=12345)
self.mux_parents = {0: 'test0', 1: 'test1', 3: 'test3'}
self.mux = Mux(name='muxe',
tree=self.tree,
parents=self.mux_parents,
mux_field=self.mux_field)
def test_get_parent(self):
parent = self.mux.get_parent()
self.assertEqual(parent.name, 'test3')
mux = Mux(name='mux',
tree=self.tree,
parents=self.mux_parents,
get_mux=ext_get_mux)
parent = mux.get_parent()
self.assertEqual(parent.name, 'test0')
def test_get_freq(self):
self.assertEqual(self.mux._get_freq(), 12345)
mux = Mux(name='pll',
tree=self.tree,
parents={
0: 'test0',
1: 'test1',
3: None
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertEqual(mux.get_freq(), 0)
def test_build(self):
mux = Mux()
self.assertFalse(mux.build())
mux = Mux(parents={0: 'parent1', 1: 'parent2'})
self.assertFalse(mux.build())
mux = Mux(parents={
0: 'parent1',
1: 'parent2'
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertFalse(mux.build())
mux = Mux(tree=self.tree,
parents={
0: 'test0',
1: 'test4'
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertFalse(mux.build())
mux = Mux(tree=self.tree,
parents={
0: 'test0',
1: 'test1'
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertTrue(mux.build())
mux = Mux(tree=self.tree,
parents={
0: 'test0',
1: 'test1',
2: None
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertTrue(mux.build())
def test_enabled(self):
mux = Mux(name='pll',
tree=self.tree,
parents={
0: 'test0',
3: None
},
mux_field=self.dev.TEST1.TESTA.A3)
self.assertFalse(mux.enabled())
self.dev.TEST1.TESTA.A3.write(0)
self.assertTrue(mux.enabled())
self.dev.TEST1.TESTA.A3.write(3)