def MOV_R_L(self, args):
a, b = str(args[0]), self.getLiteral(args[1])
b = unpack_bytes(b, Registers.sizeOf(a))
if len(b) > Registers.sizeOf(a):
raise exp.InvalidOperandSize
return regToCode[a], b
def __init__(self, tcpath, modelpath):
self._compiler = Compiler(None, None, tcpath)
self._gem5 = Gem5([], None)
self._exts = None
self._models = []
self._regs = Registers()
self._modelpath = modelpath
self._tcpath = tcpath
def __init__(self, **kwargs):
self._cached_data = {}
self.exposed_is_locked = None
super().__init__(Parameters)
from registers import Registers
self.registers = Registers(**kwargs)
self.registers.connect(self, self.parameters)
def SUB_R_L(self, args):
a, b = str(args[0]), self.getLiteral(args[1])
if ((len(hex(b)) - 2) + 0.5) > Registers.sizeOf(a):
raise exp.RegisterSizeMismatch
try:
return regToCode[str(args[0])], unpack_bytes(b, Registers.sizeOf(a))
except KeyError:
raise exp.InvalidOperandRegister
def MUL_R_R(self, args):
a, b = str(args[0]), str(args[1])
if Registers.sizeOf(a) != Registers.sizeOf(b):
raise exp.RegisterSizeMismatch
try:
return regToCode[str(args[0])], regToCode[str(args[1])]
except KeyError:
raise exp.InvalidOperandRegister
class Context(object):
def __init__(self, instructions):
self.registers = Registers()
self.flags = Flags()
self.instructions = instructions
self.heap = Memory(size=40, mode=HEAP, start_address=0x0000)
self.stack = Memory(size=40, mode=STACK, start_address=0xFFFF)
self.registers.set(SP, 0xFFFF)
def run(self):
"""
initialize the context and execute the first instruction
"""
self.registers.reset()
def step(self):
"""
execute the next instruction whose address in the EIP value
:return:
"""
self.registers.tick()
self.flags.tick()
self.heap.tick()
self.stack.tick()
next_address = self.registers.get(IP).value
if next_address < len(self.instructions):
next_instruction = self.instructions[next_address]
next_instruction.execute(self)
self.registers.set(IP, next_address + 1)
return True
else:
return False
class FrameC18n(object):
def __init__(self, path, bin_min_exp=-4, bin_max_exp=2, num_bins=None):
if not num_bins:
num_bins = 1 + bin_max_exp - bin_min_exp
self._path = path
self._img_size = self._path.stat().st_size
self._image_input = ImageInput.open(str(self._path))
if self._image_input is None:
# TODO check that the problem *is* actually the file is not there
raise FileNotFoundError(
f"could not read image `{self._path}': {oiio.geterror()}")
roi = self._image_input.spec().roi
# n.b. ROI xend and yend are range-style 'one beyond the end' values
self._x = roi.xbegin
self._width = roi.xend - roi.xbegin
self._y = roi.ybegin
self._height = roi.yend - roi.ybegin
self._overall_registers = Registers(
f"registers for entire image", "overall",
self._image_input.spec().channelnames)
self.octants = {}
for octant_key in Octant.keys():
self.octants[octant_key] = Octant(self._image_input.spec(),
octant_key, bin_min_exp,
bin_max_exp, num_bins)
def tally(self):
img_array = self._image_input.read_image()
self._overall_registers.tally(img_array,
np.full(img_array.shape[0:2], True))
for octant in self.octants.values():
octant.tally(img_array)
def add_to_columns(self, columns):
"""Append the information in the frame c18n to a Pandas DataFrame
Parameters
----------
columns : dict
"""
self._overall_registers.add_to_columns(columns)
for octant in self.octants:
self.octants[octant].add_to_columns(columns)
def summarize(self, indent_level=0):
summary = ''
summary += "overall image statistics:\n"
summary += self._overall_registers.summarize(indent_level + 1)
for octant in self.octants.values():
if samples_in_octant := octant.samples_in_octant:
summary += f"{' '*indent_level}statistics for {octant} ({samples_in_octant} samples):\n"
summary += octant.summarize(indent_level + 1)
return summary
def __init__(self):
self.taken = Signal(reset=0)
self.pre = Registers()
self.post = Registers()
self.addresses_written = Signal(3, reset=0)
self.write_addr = Array([Signal(16) for _ in range(8)])
self.write_data = Array([Signal(8) for _ in range(8)])
self.addresses_read = Signal(3, reset=0)
self.read_addr = Array([Signal(16) for _ in range(8)])
self.read_data = Array([Signal(8) for _ in range(8)])
class ProcessAndExecuteTest(unittest.TestCase):
def setUp(self):
patcher1 = patch.object(Registers, 'parse_instruction')
self.mock_parse = patcher1.start()
patcher2 = patch.object(Registers, 'is_true')
self.mock_is_true = patcher2.start()
patcher3 = patch.object(Registers, 'execute_instruction')
self.mock_execute = patcher3.start()
self.registers = Registers()
self.mock_parse.return_value = sentinel.code, sentinel.comparison
self.addCleanup(patcher1.stop)
self.addCleanup(patcher2.stop)
self.addCleanup(patcher3.stop)
def test_calls_parse_with_instruction(self):
self.registers.process_and_execute_instruction(sentinel.instruction)
self.mock_parse.assert_called_once_with(sentinel.instruction)
def test_calls_is_true_with_comparison(self):
self.registers.process_and_execute_instruction('instruction')
self.mock_is_true.assert_called_once_with(sentinel.comparison)
def test_calls_perform_instruction_only_if_is_true(self):
self.mock_is_true.return_value = True
self.registers.process_and_execute_instruction('instruction')
self.mock_execute.assert_called_once_with(sentinel.code)
self.mock_execute.reset_mock()
self.mock_is_true.return_value = False
self.registers.process_and_execute_instruction('instruction')
self.assertFalse(self.mock_execute.called)
def __init__(self, img_spec, octant_key, bin_min_exp, bin_max_exp,
num_bins):
self._img_spec = img_spec
self._octant_key = octant_key
self._to_first_octant_scalars = [-1 if e else 1 for e in octant_key]
self._edge = self._log10_edges(bin_min_exp,
bin_max_exp,
num_bins=num_bins)
self.samples_in_octant = 0
self.hist3d = np.zeros((num_bins, num_bins, num_bins), dtype=np.uint)
self._label = self.label()
register_desc = f"registers for octant {self._label}"
self._registers = Registers(register_desc, self._label,
self._img_spec.channelnames)
def setUp(self):
patcher1 = patch.object(Registers, 'parse_instruction')
self.mock_parse = patcher1.start()
patcher2 = patch.object(Registers, 'is_true')
self.mock_is_true = patcher2.start()
patcher3 = patch.object(Registers, 'execute_instruction')
self.mock_execute = patcher3.start()
self.registers = Registers()
self.mock_parse.return_value = sentinel.code, sentinel.comparison
self.addCleanup(patcher1.stop)
self.addCleanup(patcher2.stop)
self.addCleanup(patcher3.stop)
class FrameC18n(object):
def __init__(self, path, most_neg=2, least_neg=-4, num_bins=None):
if not num_bins:
num_bins = 1 + most_neg - least_neg
self._path = path
self._img_size = self._path.stat().st_size
self._image_input = ImageInput.open(str(self._path))
if self._image_input is None:
# TODO check that the problem *is* actually the file is not there
raise FileNotFoundError(
f"could not read image `{self._path}': {oiio.geterror()}")
roi = self._image_input.spec().roi
# n.b. ROI xend and yend are range-style 'one beyond the end' values
self._x = roi.xbegin
self._width = roi.xend - roi.xbegin
self._y = roi.ybegin
self._height = roi.yend - roi.ybegin
self._overall_registers = Registers(
f"rewgisters for entire image",
self._image_input.spec().channelnames)
self.octants = {}
for octant in Octant.octant_keys():
self.octants[octant] = Octant(self._image_input.spec(), octant,
most_neg, least_neg, num_bins)
def tally(self):
img_array = self._image_input.read_image()
print(f"starting overall image tally")
self._overall_registers.tally(
img_array,
np.full((self._image_input.spec().height,
self._image_input.spec().width), True))
print(f"ending overall image tally")
print(f"starting octant tallies")
for octant in self.octants.values():
print(f"starting tally for octant {octant}:")
octant.tally(img_array)
print(f"ending octant tallies")
def __str__(self):
desc = []
img_size_desc = f"{self._img_size}-byte image, {self._width*self._height*2}"
desc.append(img_size_desc)
overall_bin_desc = str(self._overall_registers)
desc.append(overall_bin_desc)
for octant in self.octants:
desc.append(str(octant))
return '\n'.join(desc)
def __init__(self, instructions):
self.registers = Registers()
self.flags = Flags()
self.instructions = instructions
self.heap = Memory(size=40, mode=HEAP, start_address=0x0000)
self.stack = Memory(size=40, mode=STACK, start_address=0xFFFF)
self.registers.set(SP, 0xFFFF)
def __init__(self, part="MSP430iua"):
assert part in CPU.CPU_TABLE
# Memoria de programa: Termina en el final del espacio de 65kB,
# y se reserva hacia abajo.
self.ROM = Memory(mem_size=self.CPU_TABLE[part][0],
mem_start=2**16 - self.CPU_TABLE[part][0],
readonly=True)
self.ROM.store_word_at(65534, self.ROM.mem_start)
# RAM inicia siempre en 0x200
self.RAM = Memory(mem_size=self.CPU_TABLE[part][1],
mem_start=0x0200,
readonly=False)
self.reg = Registers()
self.sim = Simulator(self.ROM, self.reg)
def __init__(self):
self.cmds = {
'ADD': self.add,
'ADDU': self.add,
'SUB': self.add,
'SUBU': self.add,
'OR': self.add,
'AND': self.add,
'NOR': self.add,
'XOR': self.add,
'ADDI': self.addi,
'ADDIU': self.addi,
'SUBI': self.addi,
'SUBIU': self.addi,
'ANDI': self.addi,
'ORI': self.addi,
'XORI': self.addi,
'LI': self.li,
'MOVE': self.move,
'SLT': self.slt,
'SLTU': self.slt,
'SLTI': self.slti,
'SLTIU': self.slti,
'SLL': self.sll,
'SRL': self.sll,
'J': self.j,
'JAL': self.jal,
'JR': self.jr,
'BEQ': self.beq,
'BNE': self.beq,
'MULT': self.mult,
'MULTU': self.mult,
'DIV': self.div,
'DIVU': self.div,
'MFLO': self.mfhi,
'MFHI': self.mfhi,
'NOP': self.nop,
'PYEVAL': self.pyeval,
'PYJAL': self.pycall,
'SYSCALL': self.pysyscall,
'PYEXEC': self.pyexec,
'LW': self.lw,
'SW': self.lw,
}
self.regs = Registers()
self.mem = Memory(32)
class CPU(object):
def __init__(self, dmem, imem=None):
self.r = Registers(dmem.size())
self.dmem = dmem
self.imem = imem
def start(self, debug=None):
log.info('=== CPU Start ===\n')
if debug:
last = '?'
cmds = [
'?', '(p)rint $reg', '(c)ontinue', '(d)ump', '(n)ext', '(q)uit'
]
log.info("*** debug mode enabled. '?' for help ***\n")
if self.imem is None:
raise Exception('imem not set')
while self.r.pc in xrange(len(self.imem)):
instr = self.imem[self.r.pc]
try:
log.info('[{}] {}'.format(self.r.pc, instr.raw))
self.r.pc += 1
if debug:
while True:
inp = raw_input('(debug) ').strip()
if not inp:
inp = last
else:
last = inp
if inp in ['?', 'help']:
log.info('Commands: ' + ', '.join(cmds))
elif inp in ['d', 'dump']:
self.dump()
elif inp in ['c', 'continue']:
debug = False
break
elif inp in ['n', 'next']:
break
elif inp in ['q', 'quit']:
sys.exit()
elif inp.split()[0] in ['p', 'print']:
reg = inp.split()[1]
log.info(
self.r.read(
reg[1:] if reg.startswith('$') else reg))
else:
log.error('Bad Command')
self.execute_single(instr)
except Exception, e:
if e.message == 'exit syscall':
return
raise e
log.info('\n*** pc [{}] outside instruction memory ***'.format(
self.r.pc))
def parse(args):
if len(args) != 1:
raise SyntaxError('takes only one argument, given: ' + str(len(args)))
src = args[0].strip()
if not Registers.is_register(src):
raise ValueError('not a valid register name: {0}'.format(src))
return Push(src)
class Snapshot:
def __init__(self):
self.taken = Signal(reset=0)
self.pre = Registers()
self.post = Registers()
self.addresses_written = Signal(3, reset=0)
self.write_addr = Array([Signal(16) for _ in range(8)])
self.write_data = Array([Signal(8) for _ in range(8)])
self.addresses_read = Signal(3, reset=0)
self.read_addr = Array([Signal(16) for _ in range(8)])
self.read_data = Array([Signal(8) for _ in range(8)])
def read(self, m: Module, addr: Value, data: Value):
with m.If(self.addresses_read != 7):
m.d.sync += self.addresses_read.eq(self.addresses_read + 1)
m.d.sync += self.read_addr[self.addresses_read].eq(addr)
m.d.sync += self.read_data[self.addresses_read].eq(data)
def write(self, m: Module, addr: Value, data: Value):
with m.If(self.addresses_written != 7):
m.d.sync += self.addresses_written.eq(self.addresses_written + 1)
m.d.sync += self.write_addr[self.addresses_written].eq(addr)
m.d.sync += self.write_data[self.addresses_written].eq(data)
def pre_snapshot(self, m: Module, addr: Value, data: Value, reg: Registers):
"""take a synchronous snapshot including addr and data read from ram"""
m.d.sync += [
self.taken.eq(1),
self.pre.eq(reg),
self.read_addr[0].eq(addr),
self.read_data[0].eq(data),
self.addresses_read.eq(1),
self.addresses_written.eq(0),
]
def no_snapshot(self, m: Module):
m.d.sync += self.taken.eq(0)
def post_snapshot(self, m: Module, reg: Registers):
m.d.comb += self.post.eq(reg)
def __init__(self):
self.control = Control()
self.register = Registers(32)
self.pcreg = PipelineReg()
self.if_id = PipelineReg()
self.id_exe = PipelineReg()
self.exe_mem = PipelineReg()
self.mem_wb = PipelineReg()
self.alu = Alu()
self.memory = Memory()
self.initializePipeline()
class TestRegisters(unittest.TestCase):
def setUp(self):
self.registers = Registers()
def test_access_register(self):
self.assertEqual(self.registers[0], 0)
self.assertEqual(self.registers[10], 0)
def test_change_registers(self):
self.registers[3] = 10
self.assertEqual(self.registers[3], 10)
def test_locked_register(self):
self.registers.lock(3)
self.assertRaises(RegisterInUseException, self.registers.__getitem__, 3)
def test_unlock_register(self):
self.registers[3] = 4
self.registers.lock(3)
self.registers.unlock(3)
self.assertEqual(self.registers[3], 4)
self.registers[3] = 0
self.assertEqual(self.registers[3], 0)
def test_not_number_key(self):
self.assertRaises(AttributeError, self.registers.__getitem__, "key")
self.assertRaises(AttributeError, self.registers.__setitem__, "key", "value")
def grocery(argv):
# sort customers
store = Registers()
store.load_file(argv)
store.process_customers()
print("Finished at: t={0} minutes".format(store.get_time()))
def __init__(self, path, most_neg=2, least_neg=-4, num_bins=None):
if not num_bins:
num_bins = 1 + most_neg - least_neg
self._path = path
self._img_size = self._path.stat().st_size
self._image_input = ImageInput.open(str(self._path))
if self._image_input is None:
# TODO check that the problem *is* actually the file is not there
raise FileNotFoundError(
f"could not read image `{self._path}': {oiio.geterror()}")
roi = self._image_input.spec().roi
# n.b. ROI xend and yend are range-style 'one beyond the end' values
self._x = roi.xbegin
self._width = roi.xend - roi.xbegin
self._y = roi.ybegin
self._height = roi.yend - roi.ybegin
self._overall_registers = Registers(
f"rewgisters for entire image",
self._image_input.spec().channelnames)
self.octants = {}
for octant in Octant.octant_keys():
self.octants[octant] = Octant(self._image_input.spec(), octant,
most_neg, least_neg, num_bins)
def __init__(self, program, mode = "MIPS"):
super(Assembler, self).__init__()
try: text = program.read()
except AttributeError: text = program
self.mode = mode.upper()
self.registers = Registers(self.mode)
lines = text.split("\n")
lines = clean(lines, self.mode)
instrs, data = split_sections(lines)
self.memory = Memory()
for d in data: self.memory.insert(d)
instrs = preprocess(instrs, self.mode)
self.labels = label_positions(instrs)
self.instructions = [Instruction(instr) for instr in instrs]
class TestTemporaryRegisters(unittest.TestCase):
def setUp(self):
self.registers = Registers()
self.registers[3] = 4
self.registers.lock(3)
def test_set_register_locked(self):
self.registers[3] = 2
self.assertEqual(self.registers._array[3], 4)
self.assertEqual(self.registers._tmp[3], 2)
def test_get_register_locked_without_tmp_value(self):
self.assertRaises(RegisterInUseException, self.registers.__getitem__, 3)
def test_get_register_locked_with_tmp_value(self):
self.registers[3] = 2
self.assertEqual(self.registers[3], 2)
def test_get_register_after_unlock(self):
self.registers[3] = 2
self.registers.unlock(3)
self.assertEqual(self.registers._array[3], 4)
self.registers[3] = 2
self.assertEqual(self.registers._array[3], 2)
def __init__(self, verification: Instruction = None):
self.enable = Signal(reset=1)
self.addr = Signal(16)
self.din = Signal(8)
self.dout = Signal(8)
self.RWB = Signal(reset=1) # 1 = read, 0 = write
# registers
self.reg = Registers()
self.tmp = Signal(8) # temp signal when reading 16 bits
# internal exec state
self.opcode = Signal(8)
self.cycle = Signal(4, reset=1)
# formal verification
self.verification = verification
self.snapshot = Snapshot()
def __init__(self, instructions=None, data_forwarding=False):
instructions = instructions.split("\n") if instructions else []
self.instructions = [instruction for instruction in instructions if instruction.strip()]
self.data_forwarding = data_forwarding
self.registers = Registers(size=REGISTERS_SIZE)
self.memory = Memory(size=MEMORY_SIZE)
self.history = []
self.pc = 0
self.clock = 0
self.instructions_completed = 0
self._if = InstructionFetch(self)
self._id = InstructionDecode(self)
self._ex = Execute(self)
self._mem = MemoryAccess(self)
self._wb = WriteBack(self)
self.pipeline = (self._if, self._id, self._ex, self._mem, self._wb)
def main():
from registers import Registers
m = Memory(1024, mem_start=0xfc00)
r = Registers()
s = Simulator(m, r)
m.store_words_at(0xfd00, [
0x3c55, 0x3e55, 0x1005, 0x1015, 0x0019, 0x1026, 0x1037, 0x1088, 0x1098,
0x001a, 0x10a9, 0x10b9, 0x1105, 0x1196, 0x001b, 0x122b, 0x12bc, 0x1300
])
m.store_word_at(0xfffe, 0xfd00)
print(str(m))
newpc = s.one_step(0xfffe)
print("%04x" % newpc)
newpc = s.one_step(newpc)
print("%04x" % newpc)
return 0
def test_example(self):
example_data = '\n'.join(['b inc 5 if a > 1',
'a inc 1 if b < 5',
'c dec -10 if a >= 1',
'c inc -20 if c == 10',
''])
try:
with tempfile.NamedTemporaryFile(mode='w', delete=False) as f:
f.write(example_data)
registers = Registers()
registers.parse_file(f.name)
finally:
os.remove(f.name)
self.assertEqual(registers.registers, {'a': 1, 'c': -10})
self.assertEqual(registers.get_largest_value(), 1)
self.assertEqual(registers.get_largest_value_ever_held(), 10)
class Interp:
def __init__(self):
self.cmds = {
'ADD': self.add,
'ADDU': self.add,
'SUB': self.add,
'SUBU': self.add,
'OR': self.add,
'AND': self.add,
'NOR': self.add,
'XOR': self.add,
'ADDI': self.addi,
'ADDIU': self.addi,
'SUBI': self.addi,
'SUBIU': self.addi,
'ANDI': self.addi,
'ORI': self.addi,
'XORI': self.addi,
'LI': self.li,
'MOVE': self.move,
'SLT': self.slt,
'SLTU': self.slt,
'SLTI': self.slti,
'SLTIU': self.slti,
'SLL': self.sll,
'SRL': self.sll,
'J': self.j,
'JAL': self.jal,
'JR': self.jr,
'BEQ': self.beq,
'BNE': self.beq,
'MULT': self.mult,
'MULTU': self.mult,
'DIV': self.div,
'DIVU': self.div,
'MFLO': self.mfhi,
'MFHI': self.mfhi,
'NOP': self.nop,
'PYEVAL': self.pyeval,
'PYJAL': self.pycall,
'SYSCALL': self.pysyscall,
'PYEXEC': self.pyexec,
'LW': self.lw,
'SW': self.lw,
}
self.regs = Registers()
self.mem = Memory(32)
def pcinc(self):
pc = self.regs.get('pc')
pc += 4
self.regs.set('pc', pc, special=True)
def add(self, name, d, s, t):
sval = self.regs.get(s)
tval = self.regs.get(t)
if name == 'SUB' or name == 'SUBU':
sval -= tval
elif name == 'OR':
sval |= tval
elif name == 'AND':
sval &= tval
elif name == 'XOR':
sval ^= tval
elif name == 'NOR':
sval = ~(sval | tval)
else:
sval += tval
if name == 'ADDU' or name == 'SUBU':
sval = abs(sval)
self.regs.set(d, sval)
self.pcinc()
def addi(self, name, d, s, i):
val = self.regs.get(s)
if name == 'SUBI' or name == 'SUBIU':
val -= i
elif name == 'ADDI' or name == 'ADDIU':
val += i
elif name == 'ANDI':
val &= i
elif name == 'ORI':
val |= i
elif name == 'XORI':
val ^= i
if name == 'ADDIU' or name == 'SUBIU':
val = abs(val)
self.regs.set(d, val)
self.pcinc()
def li(self, name, d, i):
self.addi('ADDI', d, '$0', i)
def move(self, name, d, s):
self.add('ADD', d, s, '$0')
def slt(self, name, d, a, b):
aval = self.regs.get(a)
bval = self.regs.get(b)
if name == 'SLTU':
aval = abs(aval)
bval = abs(bval)
if aval < bval:
val = 1
else:
val = 0
self.regs.set(d, val)
self.pcinc()
def slti(self, name, d, a, imm):
aval = self.regs.get(a)
self.regs.set(d, int(aval < imm))
self.pcinc()
def sll(self, name, d, s, i):
val = self.regs.get(s)
if i > 5:
i = 5
if name == 'SLL':
val <<= i
elif name == 'SRL':
val >>= i
self.regs.set(d, val)
self.pcinc()
def j(self, name, addr):
self.regs.set('pc', addr, special=True)
def jr(self, name, r):
self.regs.set('pc', self.regs.get(r), special=True)
def jal(self, name, addr):
self.regs.set('$ra', self.regs.get('pc') + 4)
self.j('J', addr)
def beq(self, name, a, b, addr):
aval = self.regs.get(a)
bval = self.regs.get(b)
if name == 'BEQ':
truth = (aval == bval)
elif name == 'BNE':
truth = (bval != aval)
if truth:
self.j('J', addr)
else:
self.pcinc()
def mult(self, name, a, b):
aval = self.regs.get(a)
bval = self.regs.get(b)
if name == 'MULT' or name == 'MULTU':
aval *= bval
# We're going to store high and low just cause
hi = (aval & 0xFFFFFFFF00000000) >> 0x20
lo = (aval & 0x00000000FFFFFFFF)
self.regs.set('hi', int(hi), special=True)
self.regs.set('lo', lo, special=True)
self.pcinc()
def div(self, name, a, b):
aval = self.regs.get(a)
bval = self.regs.get(b)
if name == 'DIV' or name == 'DIVU':
hi = aval / bval
lo = aval % bval
self.regs.set('hi', hi, special=True)
self.regs.set('lo', lo, special=True)
self.pcinc()
def mfhi(self, name, to):
if name == 'MFHI':
val = self.regs.get('hi')
elif name == 'MFLO':
val = self.regs.get('lo')
self.regs.set(to, val)
self.pcinc()
def nop(self, name):
self.pcinc()
def _ret_conv(self, val):
if type(val) == int:
return val
try:
res = int(val)
except:
res = 0xdeadbeef
return res
def pyeval(self, name, code):
code = code[1:-1]
res = eval(code)
if type(res) in [list, tuple]:
res0, res1 = res
res0 = self._ret_conv(res0)
res1 = self._ret_conv(res1)
self.regs.set('$v0', res0)
self.regs.set('$v1', res1)
else:
res = self._ret_conv(res)
self.regs.set('$v0', res)
self.pcinc()
def pycall(self, name, func):
args = [
self.regs.get('$a0'),
self.regs.get('$a1'),
self.regs.get('$a2'),
self.regs.get('$a3')
]
args = repr(tuple(filter(lambda x: x != 0, args)))
code = '"' + func + args + '"'
self.pyeval("PYEVAL", code)
def pyexec(self, name, code):
eval(code)
self.pcinc()
def pysyscall(self, name, func):
args = (self.regs.get('$a0'), self.regs.get('$a1'),
self.regs.get('$a2'), self.regs.get('$a3'))
code = '"' + func + '(self,' + repr(args) + ')"'
self.pyeval("PYEVAL", code)
def _addr_decode(self, addr):
import re
match = re.match("((\d+)?\((.*?)\)|(.*))", addr)
if match:
g = match.groups()
if g[1]:
offset = int(g[1])
else:
offset = 0
if g[2]:
reg = g[2]
elif g[3]:
reg = g[3]
else:
offset = 0
reg = '$0'
return offset, reg
def lw(self, name, reg, addr):
off, srcreg = self._addr_decode(addr)
addr = self.regs.get(srcreg) + off
if name == 'LW':
self.regs.set(reg, self.mem.get(addr, 4))
elif name == 'SW':
self.mem.set(addr, 4, self.regs.get(reg))
self.pcinc()
def loader(self, code):
self.mem.rom(0, code)
def execute(self, args):
inst = args[0]
self.cmds[inst](*args)
def run(self):
while True:
pc = self.regs.get('pc')
inst = self.mem.rawget(pc)
ij = []
for e in inst:
ij.append(str(e))
ij[0] = "\033[1m" + ij[0] + "\033[0m"
dbg = "\t\033[30m\033[1;34m*\033[0;37m%5d:\033[0m\t%s\033[0m\n" % (
pc, " ".join(ij))
sys.stderr.write(dbg)
self.execute(inst)
# https://c9x.me/x86/html/file_module_x86_id_219.html
def or_inst(state, inst):
parts = inst.split(' ')
op = parts[0]
lhs = parts[1][:-1]
rhs = parts[2]
"""Performs a bitwise inclusive OR operation between the destination (first) and source (second)
operands and stores the result in the destination operand location. The source operand can be an
immediate, a register, or a memory location; the destination operand can be a register or a memory
location. (However, two memory operands cannot be used in one instruction.) Each bit of the result
of the OR instruction is set to 0 if both corresponding bits of the first and second operands are 0;
otherwise, each bit is set to 1. """
"""The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined."""
return state
if __name__ == "__main__":
test_cases = ['or eax, 0x8', 'or ebx, ecx', 'or eax, ebx']
for test in test_cases:
s = Solver()
state = Registers()
state.eax = 0x7
state = or_inst(state, test)
s.add(state.eax == 0x7)
print("eax = 0x7, {}, eax == 0x7?".format(test))
if s.check() == sat:
print('Eax can be 0x7!')
print(s.model())
else:
print("Eax can't be 0x7 :(")
different; each bit is 0 if the corresponding bits are the same."""
try:
new_val = getattr(state, lhs) ^ getattr(state, rhs)
except:
new_val = getattr(state, lhs) ^ int(rhs, 16)
setattr(state, lhs, new_val)
"""The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result.
The state of the AF flag is undefined."""
state.of = False
state.cf = False
zf_state = If(getattr(state, lhs) == 0, True, False)
state.zf = zf_state
state.eip += 1
return state
if __name__ == "__main__":
examples = ['xor eax, eax', 'xor ebx, 0x8', 'xor ebx, ecx']
for example in examples:
s = Solver()
regs = Registers()
regs.ebx = 4
regs = xor(regs, example)
s.add(regs.ebx == 12)
print("ebx = 4, {}, ebx == 12?".format(example))
if s.check() == sat:
print('ebx can be 12!')
print(s.model())
else:
print("ebx can't be 12")
from registers import Registers
# https://c9x.me/x86/html/file_module_x86_id_147.html
def jmp(state, inst):
parts = inst.split(' ')
op = parts[0]
dst = int(parts[1], 16)
# Faking this since we don't really care for the examples we have
state.eip == dst
return state
if __name__ == "__main__":
s = Solver()
state = Registers()
state.eip = 0x1234
state = jmp(state, 'jmp 0x41414141')
s.add(state.eip == 0x41414141)
print('eip = 0x1234, jmp 0x41414141, eip == 0x41414141?')
check = s.check()
print(check)
print("eip == {}".format(state.eip))
s = Solver()
state = Registers()
state.eip = 0x41414141
state = jmp(state, 'jmp 0x42424242')
s.add(state.eip == 0x41414141)
check = s.check()
print('eip = 0x41414141, jmp 0x42424242, eip == 0x41414141?')
class RedPitayaControlService(BaseService):
"""Control server that runs on the RP that provides high-level methods."""
def __init__(self, **kwargs):
self._cached_data = {}
self.exposed_is_locked = None
super().__init__()
from registers import Registers
self.registers = Registers(**kwargs)
self.registers.connect(self, self.parameters)
def run_acquiry_loop(self):
"""Starts a background process that keeps polling control and error
signal. Every received value is pushed to `parameters.to_plot`."""
def data_received(is_raw, plot_data, data_uuid):
# When a parameter is changed, `pause_acquisition` is set.
# This means that the we should skip new data until we are sure that
# it was recorded with the new settings.
if not self.parameters.pause_acquisition.value:
if data_uuid != self.data_uuid:
return
data_loaded = pickle.loads(plot_data)
if not is_raw:
is_locked = self.parameters.lock.value
if not check_plot_data(is_locked, data_loaded):
print(
"warning: incorrect data received for lock state, ignoring!"
)
return
self.parameters.to_plot.value = plot_data
self._generate_signal_stats(data_loaded)
# update signal history (if in locked state)
(
self.parameters.control_signal_history.value,
self.parameters.monitor_signal_history.value,
) = update_signal_history(
self.parameters.control_signal_history.value,
self.parameters.monitor_signal_history.value,
data_loaded,
is_locked,
self.parameters.control_signal_history_length.value,
)
else:
self.parameters.acquisition_raw_data.value = plot_data
self.registers.run_data_acquisition(data_received)
self.pause_acquisition()
self.continue_acquisition()
def _generate_signal_stats(self, to_plot):
stats = {}
for signal_name, signal in to_plot.items():
stats["%s_mean" % signal_name] = np.mean(signal)
stats["%s_std" % signal_name] = np.std(signal)
stats["%s_max" % signal_name] = np.max(signal)
stats["%s_min" % signal_name] = np.min(signal)
self.parameters.signal_stats.value = stats
def exposed_write_data(self):
"""Syncs the parameters with the FPGA registers."""
self.registers.write_registers()
def task_running(self):
return (self.parameters.autolock_running.value
or self.parameters.optimization_running.value
or self.parameters.psd_acquisition_running.value
or self.parameters.psd_optimization_running.value)
def exposed_start_autolock(self,
x0,
x1,
spectrum,
additional_spectra=None):
spectrum = pickle.loads(spectrum)
# start_watching = self.parameters.watch_lock.value
start_watching = False
auto_offset = self.parameters.autolock_determine_offset.value
if not self.task_running():
autolock = Autolock(self, self.parameters)
self.parameters.task.value = autolock
autolock.run(
x0,
x1,
spectrum,
should_watch_lock=start_watching,
auto_offset=auto_offset,
additional_spectra=pickle.loads(additional_spectra)
if additional_spectra is not None else None,
)
def exposed_start_optimization(self, x0, x1, spectrum):
if not self.task_running():
optim = OptimizeSpectroscopy(self, self.parameters)
self.parameters.task.value = optim
optim.run(x0, x1, spectrum)
def exposed_start_psd_acquisition(self):
if not self.task_running():
self.parameters.task.value = PSDAcquisition(self, self.parameters)
self.parameters.task.value.run()
def exposed_start_pid_optimization(self):
if not self.task_running():
self.parameters.task.value = PIDOptimization(self, self.parameters)
self.parameters.task.value.run()
def exposed_start_ramp(self):
self.pause_acquisition()
self.parameters.combined_offset.value = 0
self.parameters.lock.value = False
self.exposed_write_data()
self.continue_acquisition()
def exposed_start_lock(self):
self.pause_acquisition()
self.parameters.lock.value = True
self.exposed_write_data()
self.continue_acquisition()
def exposed_shutdown(self):
"""Kills the server."""
self.registers.acquisition.shutdown()
_thread.interrupt_main()
# we use SystemExit instead of os._exit because we want to call atexit
# handlers
raise SystemExit
def exposed_get_server_version(self):
import linien
return linien.__version__
def exposed_get_restorable_parameters(self):
return self.parameters._restorable_parameters
def exposed_pause_acquisition(self):
self.pause_acquisition()
def exposed_continue_acquisition(self):
self.continue_acquisition()
def exposed_set_csr_direct(self, k, v):
"""Directly sets a CSR register. This method is intended for debugging.
Normally, the FPGA should be controlled via manipulation of parameters."""
self.registers.set(k, v)
def pause_acquisition(self):
"""Pause continuous acquisition. Call this before changing a parameter
that alters the error / control signal. This way, no inconsistent signals
reach the application. After setting the new parameter values, call
`continue_acquisition`."""
self.parameters.pause_acquisition.value = True
self.data_uuid = random()
self.registers.acquisition.pause_acquisition()
def continue_acquisition(self):
"""Continue acquisition after a short delay, when we are sure that the
new parameters values have been written to the FPGA and that data that
is now recorded is recorded with the correct parameters."""
self.parameters.pause_acquisition.value = False
self.registers.acquisition.continue_acquisition(self.data_uuid)
class Mips(object):
def __init__(self, instructions=None, data_forwarding=False):
instructions = instructions.split("\n") if instructions else []
self.instructions = [instruction for instruction in instructions if instruction.strip()]
self.data_forwarding = data_forwarding
self.registers = Registers(size=REGISTERS_SIZE)
self.memory = Memory(size=MEMORY_SIZE)
self.history = []
self.pc = 0
self.clock = 0
self.instructions_completed = 0
self._if = InstructionFetch(self)
self._id = InstructionDecode(self)
self._ex = Execute(self)
self._mem = MemoryAccess(self)
self._wb = WriteBack(self)
self.pipeline = (self._if, self._id, self._ex, self._mem, self._wb)
def run(self, life=MIPS_MAX_AGE):
while True:
self.history.append(self.current_state())
self.execute_pipeline()
self.clock += 1
if self.clock > life or (all(isinstance(p.instruction, StallInstruction) for p in self.pipeline) and self.pc == 4 * len(self.instructions)):
self.history.append(self.current_state())
break
def _go_forward_pipeline(self):
if self.pipeline[4].done:
self.pipeline[4].instruction = None
for a, b in reversed(zip(self.pipeline[:-1], self.pipeline[1:])):
if a.done and b.instruction is None:
b.instruction = a.instruction
a.instruction = None
def execute_pipeline(self):
self._go_forward_pipeline()
for phase in self.pipeline:
phase.execute()
if not phase.instruction:
phase.instruction = StallInstruction()
def jump(self, pc):
self._if.instruction.unlock_registers(self)
self._if.instruction = StallInstruction()
self._id.instruction.unlock_registers(self)
self._id.instruction = StallInstruction()
self.pc = pc
def current_state(self):
instructions_completed = self.instructions_completed
throughput = instructions_completed / self.clock if self.clock > 0 else 0
state = {"pipeline":[p.instruction.current_state() for p in self.pipeline],
"registers":self.registers.current_state(),
"memory":self.memory.history[-4:],
"clock":self.clock,
"pc":self.pc,
"instructions_completed":instructions_completed,
"throughput":throughput}
return state
class Parser:
'''
This class stepwise calls all the functions necessary to parse modules
and retrieve the information necessary to extend gnu binutils and gem5.
'''
def __init__(self, tcpath, modelpath):
self._compiler = Compiler(None, None, tcpath)
self._gem5 = Gem5([], None)
self._exts = None
self._models = []
self._regs = Registers()
self._modelpath = modelpath
self._tcpath = tcpath
def restore(self):
'''
Restore the toolchain to its defaults.
'''
logger.info('Remove custom instructions from GNU binutils files')
self._compiler.restore()
self._gem5.restore()
def parse_models(self):
'''
Parse the c++ reference implementation
of the custom instruction.
'''
logger.info('Determine if modelpath is a folder or a single file')
if os.path.isdir(self._modelpath):
# restore the toolchain to its defaults
self.restore()
logger.info('Traverse over directory')
self.treewalk(self._modelpath)
else:
logger.info('Single file, start parsing')
model = Model(self._modelpath)
self._models.append(model)
# add model for read function
self._models.append(Model(read=True))
# add model for write function
self._models.append(Model(write=True))
self._exts = Extensions(self._models)
self._compiler = Compiler(self._exts, self._regs, self._tcpath)
self._gem5 = Gem5(self._exts, self._regs)
def treewalk(self, top):
logger.info('Search for models in {}'.format(top))
logger.debug('Directory content: {}'.format(os.listdir(top)))
for file in os.listdir(top):
pathname = os.path.join(top, file)
mode = os.stat(pathname)[ST_MODE]
if S_ISDIR(mode):
# directory
self.treewalk(pathname)
elif S_ISREG(mode):
# file
if pathname.endswith('.cc'):
logger.info('Model definition in file {}'.format(pathname))
model = Model(pathname)
self._models.append(model)
# registers
if pathname.endswith('registers.hh'):
logger.info('Custom registers in file {}'.format(pathname))
self._regs.parse_file(pathname)
else:
# unknown file type
logger.info('Unknown file type, skip')
def extend_compiler(self):
'''
Extend the riscv compiler.
'''
self._compiler.extend_compiler()
def extend_gem5(self):
'''
Extend the gem5 simulator.
'''
self._gem5.extend_gem5()
@property
def args(self):
return self._args
@property
def compiler(self):
return self._compiler
@property
def decoder(self):
return self._gem5
@property
def extensions(self):
return self._exts
@property
def models(self):
return self._models
@property
def regs(self):
return self._regs
class Pipelinecpu(object):
'''This class is the pipelinecpu'''
def __init__(self):
self.control = Control()
self.register = Registers(32)
self.pcreg = PipelineReg()
self.if_id = PipelineReg()
self.id_exe = PipelineReg()
self.exe_mem = PipelineReg()
self.mem_wb = PipelineReg()
self.alu = Alu()
self.memory = Memory()
self.initializePipeline()
def getRegisterState(self):
return self.register.getRegisterState()
def getInstructionCount(self):
return self.instructionCount
def getDataCount(self):
return self.dataCount
def getInstruction(self, i):
return self.memory.readMemory(i)
def readMemory(self, i):
return self.memory.readMemory(i)
def getPC(self):
return self.pc
def initializePipeline(self):
## Deletes memory and instruction count
self.signalWPC = 1
self.signalWIR = 1
self.regData = 0
self.pc = 0
self.signalBtaken = 0
self.signalSld = 0
self.signalWreg = 0
self.signalLOADDEPEN = 1
self.inst = ''
self.signalShift = 0
self.tempinst = ''
## Initializes Registers
self.memory.initialize()
self.register.initialize()
self.pcreg.initialize()
self.if_id.initialize()
self.id_exe.initialize()
self.exe_mem.initialize()
self.mem_wb.initialize()
## Forwarding Unit
def __forwardingUnit(self):
int2 = functools.partial(int, base=2)
self.rs1IsReg = (self.opcode != int2(opcodes['bne'])) & (self.opcode != int2(opcodes['beq'])) & (
self.opcode != int2(opcodes['branch']))
self.rs2IsReg = (self.opcode == int2(opcodes['and'])) | (self.opcode == int2(opcodes['or'])) | (
self.opcode == int2(opcodes['add'])) | \
(self.opcode == int2(opcodes['sub'])) | (self.opcode == int2(opcodes['sra'])) | (
self.opcode == int2(opcodes['sll'])) | \
(self.opcode == int2(opcodes['srl']))
# ALU A select signal
ADEPEN1 = ((self.exe_mem.signalWreg == 1) & (self.readReg1 == self.exe_mem.regD) | (self.mem_wb.signalWreg == 1) & \
(self.readReg1 == self.mem_wb.regD)) & (self.rs1IsReg)
ADEPEN2 = ((self.mem_wb.signalWreg == 1) & (self.readReg1 == self.mem_wb.regD)) & (self.rs1IsReg)
self.signalADEPEN = ADEPEN1 * 2 + ADEPEN2
#ALU B select signal
BDEPEN1 = ((self.exe_mem.signalWreg == 1) & (self.readReg2 == self.exe_mem.regD) | (self.mem_wb.signalWreg == 1) & \
(self.readReg2 == self.mem_wb.regD)) & (self.rs2IsReg)
BDEPEN2 = (self.mem_wb.signalWreg == 1) & (self.readReg2 == self.mem_wb.regD) & (self.rs2IsReg) | (
not self.rs2IsReg)
self.signalBDEPEN = BDEPEN1 * 2 + BDEPEN2
#LOADDEPEN
EXE_A_DEPEN = (self.readReg1 == self.exe_mem.regD) & (self.exe_mem.signalSld == 1) & (self.rs1IsReg)
EXE_B_DEPEN = (self.readReg2 == self.exe_mem.regD) & (self.exe_mem.signalSld == 1) & (self.rs2IsReg) | \
(self.readReg2 == self.exe_mem.regD) & (self.exe_mem.signalSld == 1) & (self.opcode == int2(opcodes['store']))
self.signalLOADDEPEN = not (EXE_A_DEPEN | EXE_B_DEPEN)
#STORE
self.signalQDEPEN = (self.readReg2 == self.exe_mem.regD) & (self.exe_mem.signalWreg == 1)
## Instruction Fetch Stage
def __cpuStageIF(self, bin_instruction, instruction):
self.signalBtaken = self.control.getBtaken()
if self.signalBtaken:
self.nextPC = twos_to_int(self.if_id.instruction & 0x3FFFFFF, 26)
else:
self.nextPC = self.pc + 1
int2 = functools.partial(int, base=2)
if self.opcode == 10 or self.opcode == 11:
self.signalWPC = not(((self.opcode == int2(opcodes['bne'])) | (self.opcode == int2(opcodes['beq']))) & \
self.exe_mem.signalWreg & (not self.exe_mem.signalSld))
self.signalWPC = int(self.signalWPC)
self.signalWIR = self.signalWPC
else:
if self.signalLOADDEPEN | (self.opcode == 9): #not loaddepen or after load is store
self.signalWPC = 1
self.signalWIR = 1
else:
self.signalWIR = 0
self.signalWPC = 0
'''
elif self.opcode == 9:
self.signalWPC = not(self.exe_mem.signalWreg & (self.exe_mem.signalSld |self.exe_mem.regD == self.readReg2))
self.signalWPC = int(self.signalWPC)
self.signalWIR = self.signalWPC
'''
if self.signalWPC:
self.pc = self.nextPC
else:
self.pc = self.pc
if self.signalWIR:
self.if_id.instruction = bin_instruction
self.if_id.inst = instruction
else:
self.if_id.instruction = self.if_id.instruction
self.if_id.inst = self.if_id.inst
return self.pc
## Instruction Decode Stage
def __cpuStageID(self):
#self.id_exe = self.if_id # Pipeline shift
## instruction Decode
self.opcode = (self.if_id.instruction & 0xFC000000) >> 26 # inst[31:26]
# Sets control based on opcode and zeroResult
self.control.signalIn(self.opcode, self.exe_mem.zeroResult)
self.readReg1 = (self.if_id.instruction & 0x001F0000) >> 16 # inst[20:16]
if self.control.getSst(): # store
self.readReg2 = (self.if_id.instruction & 0x03E00000) >> 21 #inst[25:21]
else:
self.readReg2 = (self.if_id.instruction & 0x0000001F) # inst[4:0]
# Forwarding Detect
self.__forwardingUnit()
self.id_exe.regD = ((self.if_id.instruction & 0x03E00000) >> 21) # rd
# Sets ID_EXE registers based on register data
self.signalShift = self.control.getShift()
if self.signalShift:
self.id_exe.readData1 = self.readReg1 # sa for shift instructions
else:
self.id_exe.readData1 = self.register.readRegister(self.readReg1)
self.id_exe.readData2 = self.register.readRegister(self.readReg2)
# Stores the necessary control bits in ID_EXE registers
self.id_exe.signalisStore = self.control.getisSTORE()
self.id_exe.signalBtaken = self.control.getBtaken()
self.id_exe.signalQDEPEN = int(self.signalQDEPEN)
self.id_exe.signalADEPEN = self.signalADEPEN
#print 'ADEPEN', self.id_exe.signalADEPEN
self.id_exe.signalBDEPEN = self.signalBDEPEN
#print 'BDEPEN', self.id_exe.signalBDEPEN
self.id_exe.signalAluOp = self.control.getAluOp()
#print 'ALUOP', self.id_exe.signalAluOp
self.id_exe.signalWz = self.control.getWz() & (self.signalLOADDEPEN | (self.opcode == 9)) & (not self.exe_mem.signalBtaken)
self.id_exe.signalWreg = self.control.getWreg() & (self.signalLOADDEPEN | (self.opcode == 9)) & (not self.exe_mem.signalBtaken)
self.id_exe.signalWmem = self.control.getWmem() & (self.signalLOADDEPEN | (self.opcode == 9)) & (not self.exe_mem.signalBtaken)
self.id_exe.signalSld = self.control.getSld()
self.id_exe.inst = self.if_id.inst
# Sets ID_EXE registers immediateValue based on control signal sext
if self.control.getSext():
self.id_exe.immediateValue = twos_to_int(self.if_id.instruction & 0xFFFF, 16)
else:
self.id_exe.immediateValue = self.if_id.instruction & 0xFFFF
self.istransfer = (self.opcode == 10 or self.opcode == 11 or self.opcode == 12)
self.iswrite = (self.id_exe.signalWreg or self.id_exe.signalWmem)
if (not self.istransfer) & self.iswrite:
self.tempinst = self.id_exe.inst
elif self.istransfer & (self.exe_mem.inst == 'stall'):
self.tempinst = self.id_exe.inst
elif self.id_exe.inst == '':
self.tempinst = self.id_exe.inst
elif self.istransfer & (self.opcode == 12):
self.tempinst = self.id_exe.inst
else:
self.tempinst = 'stall'
## Instruction Execution Stage
def __cpuStageEXE(self):
self.exe_mem.inst = self.tempinst
self.exe_mem.signalisStore = self.id_exe.signalisStore
self.exe_mem.signalBtaken = self.id_exe.signalBtaken
self.exe_mem.signalADEPEN = self.id_exe.signalADEPEN
self.exe_mem.signalBDEPEN = self.id_exe.signalBDEPEN
self.exe_mem.signalAluOp = self.id_exe.signalAluOp
self.exe_mem.readData2 = self.id_exe.readData2
self.exe_mem.regD = self.id_exe.regD
self.exe_mem.signalWmem = self.id_exe.signalWmem
self.exe_mem.signalWreg = self.id_exe.signalWreg
self.exe_mem.signalSld = self.id_exe.signalSld
self.exe_mem.signalWz = self.id_exe.signalWz
# forwarding
if self.id_exe.signalADEPEN == 0:
self.aluA = self.id_exe.readData1
elif self.id_exe.signalADEPEN == 2:
self.aluA = self.exe_mem.aluResult
elif self.id_exe.signalADEPEN == 3:
self.aluA = self.regData
else:
print 'Error!'
if self.id_exe.signalBDEPEN == 0:
self.aluB = self.id_exe.readData2
elif self.id_exe.signalBDEPEN == 1:
self.aluB = self.id_exe.immediateValue
elif self.id_exe.signalBDEPEN == 2:
self.aluB = self.mem_wb.aluResult
elif self.id_exe.signalBDEPEN == 3:
self.aluB = self.regData
else:
print 'Error!'
'''
if self.exe_mem.signalQDEPEN == 0:
self.storeD = self.id_exe.readData2
elif self.exe_mem.signalQDEPEN == 1:
self.storeD = self.regData
else:
print 'Error!'
'''
self.exe_mem.signalQDEPEN = int(self.id_exe.signalQDEPEN)
#self.exe_mem.storeD = self.storeD
self.alu.compute(self.id_exe.signalAluOp, self.aluA, self.aluB)
## Sets EXE_MEM registers
self.exe_mem.aluResult = self.alu.getResults()
if self.id_exe.signalWz:
self.exe_mem.zeroResult = self.alu.getZero()
## Memory Stage
def __cpuStageMEM(self):
self.mem_wb.inst = self.exe_mem.inst
self.mem_wb.regD = self.exe_mem.regD
self.mem_wb.readData2 = self.exe_mem.readData2
self.mem_wb.aluResult = self.exe_mem.aluResult
self.mem_wb.signalSld = self.exe_mem.signalSld
self.mem_wb.signalWreg = self.exe_mem.signalWreg
self.mem_wb.signalWmem = self.exe_mem.signalWmem
if self.exe_mem.signalQDEPEN == 0:
self.storeD = self.exe_mem.readData2
elif self.exe_mem.signalQDEPEN == 1:
self.storeD = self.regData
else:
print 'Error!'
self.mem_wb.signalQDEPEN = self.exe_mem.signalQDEPEN
## Read from Memory
self.mem_wb.memReadData = self.memory.readMemory(self.exe_mem.aluResult)
## Write to Memory
if self.exe_mem.signalWmem:
self.memory.writeMemory(int_to_twos(self.exe_mem.aluResult), self.storeD)
## Write Back Stage
def __cpuStageWB(self):
self.inst = self.mem_wb.inst
self.signalWreg = self.mem_wb.signalWreg
self.signalSld = self.mem_wb.signalSld
if self.signalSld:
self.regData = self.mem_wb.memReadData
else:
self.regData = self.mem_wb.aluResult
if self.signalWreg:
self.register.writeRegister(self.mem_wb.regD, self.regData)
def atomicStep(self, bin_instruction, instruction):
self.__cpuStageWB()
self.__cpuStageMEM()
self.__cpuStageEXE()
self.__cpuStageID()
return self.__cpuStageIF(bin_instruction, instruction)
def mul_reg_reg(self):
a = self.program_scanner.nextRegister()
b = self.program_scanner.nextRegister()
c = self.registers.get(a) * self.registers.get(b)
self.registers.set(Registers.nextSize(a), c)
def sub_reg_lit(self):
a = self.program_scanner.nextRegister()
b = self.program_scanner.nextBytes(Registers.sizeOf(a))
c = self.registers.get(a) - b
self.registers.set(a, c)
def mov_reg_lit(self):
a = self.program_scanner.nextRegister()
b = self.program_scanner.nextBytes(Registers.sizeOf(a))
self.registers.set(a, b)
except socket.timeout:
logging.warning("connection to %s has timed out" % str(client_address))
finally:
logging.info("closing connection to %s" % str(client_address))
connection.close()
if __name__ == "__main__":
logging.basicConfig(filename='aor_lookup.log',
level=logging.DEBUG,
format='%(asctime)s %(levelname)s %(message)s')
logging.info("starting up the server")
registers = Registers()
registers.from_file(REGISTRATION_FILEPATH)
sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
server_address = ('', PORT)
sock.bind(server_address)
sock.listen(1)
logging.info("listening on port %d" % PORT)
while True:
connection, client_address = sock.accept()
logging.info("accepted connection from %s" % str(client_address))
connection.settimeout(CONNECTION_TIMEOUT)
logging.info("starting new thread to process request from %s" %
str(client_address))
def __init__(self, dmem, imem=None):
self.r = Registers(dmem.size())
self.dmem = dmem
self.imem = imem
def setUp(self):
self.registers = Registers()
self.registers[3] = 4
self.registers.lock(3)
op = parts[0]
dst = int(parts[1], 16)
"""
mnemonic Description signed conditions
JNE Jump if not equal N/A ZF = 0
JNZ Jump if not zero N/A ZF = 0
"""
new_eip = If(state.zf == False, dst, state.eip + 1)
state.eip = new_eip
return state
if __name__ == "__main__":
s = Solver()
state = Registers()
state.zf = False
state.eip = 0x1234
state = jnz(state, 'jnz 0x41414141')
s.add(state.eip == 0x41414141)
check = s.check()
print('zf = False, eip = 0x1234, jnz 0x41414141, eip == 0x41414141?')
print(check)
s = Solver()
state = Registers()
state.zf = True
state.eip = 0x41414141
state = jnz(state, 'jnz 0x42424242')
s.add(state.eip == 0x41414141)
check = s.check()
def setUp(self):
self.registers = Registers()
class Octant(object):
"""
Class to hold spatial and statistical distribution of pixel values in a Cartesian octant.
Parameters
----------
img_spec : OpenImageIO ImageSpec
Describes the image to be analyzed
octant_key : tuple of booleans
Indicates whether an octant axis represents, in the space of pixel values, distance
along the negative extent of that axis. (All octant data is stored with spatial
and statistical data transformed to all-positive values; for the spatial data, the
_to_first_octant_scalars attribute provides for transformatipon back to the original
coordinate system.
bin_min_exp : int
Base-10 exponent of the largest negative value considered to not be 'overflow'. See
documentation of the LogBins class for the gory details.
bin_max_exp : int
Base-10 exponent of the tinyest negative value considered to not be 'underflow'. See
documentaionm of the LogBinds class for the gory details.
num_bins : int
Number of bins into which pixel values will be mapped
"""
@staticmethod
def keys():
keys = []
for has_blue_neg in (False, True):
for has_green_neg in (False, True):
for has_red_neg in (False, True):
keys.append((has_red_neg, has_green_neg, has_blue_neg))
return keys
def _name(self, channel_names, spacer):
name_pieces = []
negativities_and_names = zip(self._octant_key, channel_names)
for negativity, name in negativities_and_names:
name_pieces += [f"{name}{'-' if negativity else '+'}"]
return spacer.join(name_pieces)
def name(self):
return self._name(['red', 'green', 'blue'], ', ')
def label(self):
return f"oct_{self._name(['r', 'g', 'b'], '')}"
def _ix_for_octant(self, img_array):
ix = np.full(img_array.shape[:2], True, dtype=np.bool)
for chan, axis_negative_in_octant in enumerate(self._octant_key):
chan_in_octant_ix = img_array[
...,
chan] < 0 if axis_negative_in_octant else img_array[...,
chan] >= 0
np.logical_and(ix, chan_in_octant_ix, ix)
return ix
@staticmethod
def _log10_edges(min_exp, max_exp, num_bins=None):
if not num_bins:
num_bins = 1 + max_exp - min_exp
zero_anchor = np.array([0])
edge = 10**(np.linspace(min_exp,
max_exp,
num_bins,
dtype=np.dtype('half')))
max_anchor = np.array([np.finfo('half').max])
edge = np.hstack([zero_anchor, edge, max_anchor])
return edge
def __init__(self, img_spec, octant_key, bin_min_exp, bin_max_exp,
num_bins):
self._img_spec = img_spec
self._octant_key = octant_key
self._to_first_octant_scalars = [-1 if e else 1 for e in octant_key]
self._edge = self._log10_edges(bin_min_exp,
bin_max_exp,
num_bins=num_bins)
self.samples_in_octant = 0
self.hist3d = np.zeros((num_bins, num_bins, num_bins), dtype=np.uint)
self._label = self.label()
register_desc = f"registers for octant {self._label}"
self._registers = Registers(register_desc, self._label,
self._img_spec.channelnames)
def _bin(self, img_array, octant_ix):
bins = [self._edge] * 3
img_in_octant = img_array[octant_ix]
img_in_octant *= self._to_first_octant_scalars
self.hist3d, _ = np.histogramdd(img_in_octant, bins)
def tally(self, img_array):
octant_ix = self._ix_for_octant(img_array)
self.samples_in_octant = np.sum(octant_ix)
self._bin(img_array, octant_ix)
self._registers.tally(img_array, octant_ix)
def add_to_columns(self, columns):
self._registers.add_to_columns(columns)
def summarize(self, indent_level=0):
return self._registers.summarize(indent_level)
except:
new_val = old_val + int(rhs, 16)
setattr(state, lhs, new_val)
"""The OF, SF, ZF, AF, CF, and PF flags are set according to the result."""
state.of = If(new_val < old_val, True, False)
state.cf = If((((old_val >> 31) & 1) ^ ((new_val >> 31) & 1)) == 1, True, False)
zf_state = If(new_val == 0, True, False)
state.zf = zf_state
sf_state = If(new_val < 0, True, False)
state.sf = sf_state
state.eip += 1
return state
if __name__ == "__main__":
examples = ['add eax, 0x8', 'add esp, 0x4', 'add eax, ebx']
for example in examples:
s = Solver()
regs = Registers()
regs.eax = 0xf4
regs = add(regs, example)
s.add(regs.sf == False)
print("eax == 0xf4, {}, sf == False?".format(example))
check = s.check()
print(check)
if check == sat:
print("Model: {}".format(s.model()))
#!python
# imports do sistema do python
import sys
import re
# criados por nos
from instructions import Instructions
from registers import Registers
instr = Instructions()
regs = Registers()
# parse dos registradores
def parse_immediate(line):
line = line.split()
for i, token in enumerate(line):
# ignore a instrucao e os registradores,
# processe somente numeros decimais
# (imediatos e numeros crus)
if (i == 0 or token[0] == 'r'):
continue
# verifique o tamanho final das palavra
word_size = (5 if i < 3 else 16)
# altere o token (que e um numero)
token = bin(int(token))[2:]
# faca o prepend de zeros na frente do token pra que
# ele tenha o tamanho correto
line[i] = '0' * (word_size - len(token)) + token
return ' '.join(line)
def get_hex_input():
try_again = True
while try_again:
hex = input("Enter an instruction: ")
parameter_one = is_hex(hex)
parameter_two = is_8_values_long(hex)
if (parameter_one == True and parameter_two == True):
try_again = False
else:
print("Enter a hexadecimal instruction with 8 characters")
return hex
registers = Registers()
memory = Memory(50)
convertor = Convertor()
print_registers_and_memory(registers, memory)
on = True
while on:
instruction = get_hex_input()
'''
00430825 - or $1,$2,$3
00430820 - add $1,$2,$3
00430822 - sub $1,$2,$3
00430829 - and $1,$2,$3
00430826 - xor $1,$2,$3
20410003 - addi $1,$2,3
def mov_reg_mem(self):
a = self.program_scanner.nextRegister()
b = self.program_scanner.nextMemory()
print(b)
b = self.memory[b:b + Registers.sizeOf(a)]
self.registers.set(a, pack_bytes(b))
def nextRegister(self): a = self.nextBytes(REGISTER_SIZE) return Registers.codeToName(a)
