def dac_sawtooth_test():
#reps = 5000000000/2 #about 10 seconds
reps = 16
#Create a new high level board object and some channels
board_obj = rbd.rfsoc_board(portname)
#locking_filename = "test_waveforms\\tdcsq.txt"
locking_filename = ""
#waveform_filename = "test_waveforms\\testw2.txt"
waveform_filename = "C:\james\RFSoC_Controller_V2\python_source\\test_waveforms\\testw2.txt"
c0 = rbd.rfsoc_channel("DAC", 0, 0, 1, 8 + 0, 32, 4, reps, 1,
waveform_filename, locking_filename, 0, 0)
c1 = rbd.rfsoc_channel("DAC", 1, 0, 1, 8 + 0.25, 32, 4, reps, 1,
waveform_filename, locking_filename, 0, 0)
c2 = rbd.rfsoc_channel("DAC", 2, 0, 1, 8 + 0.5, 32, 4, reps, 1,
waveform_filename, locking_filename, 0, 0)
c3 = rbd.rfsoc_channel("DAC", 3, 0, 1, 8 + 0.75, 32, 4, reps, 1,
waveform_filename, locking_filename, 0, 0)
c4 = rbd.rfsoc_channel("DAC", 4, 0, 1, 8 + 1, 32, 4, reps, 1,
waveform_filename, locking_filename, 0, 0)
board_obj.channel_list.append(c0)
board_obj.channel_list.append(c1)
board_obj.channel_list.append(c2)
board_obj.channel_list.append(c3)
board_obj.channel_list.append(c4)
#wp.plot_dac_waveforms(board_obj.channel_list)
#Check the status of the clocks
board_obj.board_driver.open_board()
if (board_obj.board_driver.reset_fabric()):
raise RuntimeError("Error resetting FPGA fabric")
dac_status, adc_status = board_obj.board_driver.check_clocks()
board_obj.board_driver.close_board()
if (dac_status):
raise RuntimeError(
"Error, the DAC RF clock for the FPGA was not detected, cannot upload waveforms without an RF clock present"
)
#Configure the board
if (board_obj.configure_all_channels()):
raise RuntimeError("Error, could not configure channels for DAC test")
#Trigger the board once
if (board_obj.trigger()):
raise RuntimeError("Error triggering board")
#if(board_obj.trigger()):
#raise RuntimeError("Error triggering board")
return 0
def setup_channel_list(self, waveform, chann_num, coarse_delay):
chan = rbd.rfsoc_channel("DAC", chann_num, 0, 0, 0, 0, 8, 1, 1, "", "",
0, 0)
chan.mask_enable = 0
chan.waveform_samples = waveform
chan.run_cycles = int(len(waveform) / 16)
chan.pre_delay_cycles = coarse_delay
chan.post_delay_cycles = 16
return chan
import rfsoc_board_driver as rbd
portname = "COM15"
board_obj = rbd.rfsoc_board(portname)
scale = 0.5
#generate our test waveform for a single pulse
wave_single_pulse = [round(rbd.DAC_MAX_VALUE * scale)] * 8 + [0] * 8 + [0] * 64
single_pulse_cycles = round(len(wave_single_pulse) / 16)
#Set up our test channel
chan = rbd.rfsoc_channel("DAC", 4, 0, 0, 0, 0, 8, 1, 1, "", "", 0, 0)
chan.waveform_samples = wave_single_pulse
chan.run_cycles = single_pulse_cycles
#Add the test channel to the board object
board_obj.channel_list = [chan]
#Configure the board
if (board_obj.configure_all_channels()):
raise RuntimeError("Error, could not configure channels for amp test")
print("Press any key to trigger board for single pulse test")
dummy = input()
#Trigger the board once
if (board_obj.trigger()):
raise RuntimeError("Error triggering board")
#Load the board state
board = rbd.load_rfsoc_board()
#Add an ADC channel (or append the current one)
found = 0
for c in board.channel_list:
if (c.type == "ADC"):
found = 1
c.shift_val = adc_shift
c.adc_run_cycles = adc_run_cycles
c.check_parameters()
break
#If we need to add an adc channel
if (found == 0):
c = rbd.rfsoc_channel("ADC", 0, 0, 0, 0, 0, 0, 0, 0, "", "", adc_shift,
adc_run_cycles)
board.channel_list.append(c)
#Check the status of the clocks
board.board_driver.open_board()
d0, d1, d2, d3, a0, a1, a2, a3 = board.board_driver.check_clocks(full_stats=1)
board.board_driver.close_board()
ds = [d0, d1, d2, d3]
if (d0):
raise RuntimeError(
"Error, the DAC RF clock for channels 1-4 was not detected, cannot upload waveforms without an RF clock present"
)
if (a0 and adc_run_cycles != 0):
raise RuntimeError(
"Error, the ADC RF clock for the FPGA was not detected, cannot use ADC without clock"
)
square_wave = [rbd.DAC_MAX_VALUE] * 8 + [rbd.DAC_MIN_VALUE] * 8
for i in range(0, num_pulses):
scale = (i + 1) / num_pulses
d_w = [e * scale for e in square_wave]
dac_wave += d_w
#Add the delay in
dac_wave = [0] * dac_delay + dac_wave + [0] * (16 - dac_delay)
#Cast everything to int to avoid later problems
for i in range(0, len(dac_wave)):
dac_wave[i] = int(dac_wave[i])
#set up the dac channel
d_chan = rbd.rfsoc_channel("DAC", dac_chan_num, 0, 0, 0, 0, 8, 1, 1, "", "", 0,
0)
d_chan.mask_enable = 0
d_chan.waveform_samples = dac_wave
d_chan.run_cycles = int(len(dac_wave) / 16)
d_chan.pre_delay_cycles = dac_pre_delay
d_chan.post_delay_cycles = 16
#set up the adc channel
a_chan = rbd.rfsoc_channel("ADC", adc_channel_num, 0, 0, 0, 0, 0, 0, 0, "", "",
adc_shift, adc_run_cycles)
#Create the driver object
board_obj = rbd.rfsoc_board(portname)
#Add the ADC and DAC channels to the board driver
board_obj.channel_list = [a_chan, d_chan]
i_wave += [val_i]*8 + [val_i*-1]*8
#Finalize the waveforms with the correct delays
i_c = int(i_del/16)
q_c = int(q_del/16)
i_del = i_del % 16
q_del = q_del % 16
i_wave_f = [0]*i_del + i_wave + [0]*(16-i_del)
q_wave_f = [0]*q_del + q_wave + [0]*(16-q_del)
#Board object to be used
board_obj = rbd.rfsoc_board(portname)
#Set up the channel object
i_chan = rbd.rfsoc_channel("DAC", i_chan_num, 0, 0, 0, 0, 8, 1, 1, "", "", 0, 0)
i_chan.mask_enable = 0
i_chan.waveform_samples = i_wave_f
i_chan.run_cycles = int(len(i_wave)/16);
i_chan.pre_delay_cycles = i_c
i_chan.post_delay_cycles = 16
#Set up the channel object
q_chan = rbd.rfsoc_channel("DAC", q_chan_num, 0, 0, 0, 0, 8, 1, 1, "", "", 0, 0)
q_chan.mask_enable = 0
q_chan.waveform_samples = q_wave_f
q_chan.run_cycles = int(len(q_wave)/16);
q_chan.pre_delay_cycles = q_c
q_chan.post_delay_cycles = 16
#Add the channels to the rfsoc object
def run_exp_list(self, a_im, a_pm, b_im, b_pm, c_im, c_pm, a_atten, a_del,
b_del, c_del, adc_avgs):
if (a_del > 4 or b_del > 4 or c_del > 4 or a_del < 0 or b_del < 0
or c_del < 0):
raise ValueError(
"Error, channel delay must be less than 4ns and greater or equal to 0ns"
)
#If our adc averages is 0 or not a power of 2
if (adc_avgs == 0
or math.log(adc_avgs, 2) != round(math.log(adc_avgs, 2))):
raise ValueError(
"Error, adc averages must be greater than 0 and a power of 2")
if (USE_IQ):
#TODO
return
#Deal with channel A first
a_im_wave, a_im_del = self.get_waveform_list(a_im, a_del)
a_pm_wave, a_pm_del = self.get_waveform_list(a_pm, a_del)
a_im_chan = self.setup_channel_list(a_im_wave, self.a_im_channel_num,
a_im_del)
a_pm_chan = self.setup_channel_list(a_pm_wave, self.a_pm_channel_num,
a_pm_del)
b_im_wave, b_im_del = self.get_waveform_list(b_im, b_del)
b_pm_wave, b_pm_del = self.get_waveform_list(b_pm, b_del)
b_im_chan = self.setup_channel_list(b_im_wave, self.b_im_channel_num,
b_im_del)
b_pm_chan = self.setup_channel_list(b_pm_wave, self.b_pm_channel_num,
b_pm_del)
c_im_wave, c_im_del = self.get_waveform_list(c_im, c_del)
c_pm_wave, c_pm_del = self.get_waveform_list(c_pm, c_del)
c_im_chan = self.setup_channel_list(c_im_wave, self.c_im_channel_num,
c_im_del)
c_pm_chan = self.setup_channel_list(c_pm_wave, self.c_pm_channel_num,
c_pm_del)
a_atten_wave, a_atten_del = self.get_waveform_list(a_atten, a_del)
a_atten_chan = self.setup_channel_list(a_atten_wave,
self.a_atten_channel_num,
a_atten_del)
#Add the ADC channel
adc_chan = rbd.rfsoc_channel("ADC", self.adc_channel_num, 0, 0,
0, 0, 8, 1, 1, "", "",
math.log(adc_avgs, 2), 32)
#Clear anything that's currently in the board object and add our channels
self.board_obj.channel_list = [
a_im_chan, a_pm_chan, b_im_chan, b_pm_chan, c_im_chan, c_pm_chan,
a_atten_chan, adc_chan
]
#Check the status of the clocks
self.board_obj.board_driver.open_board()
dac0, dac1, dac2, dac3, adc0, adc1, adc2, adc3 = self.board_obj.board_driver.check_clocks(
full_stats=1)
self.board_obj.board_driver.close_board()
if (dac0 or dac1):
raise RuntimeError(
"Error, the DAC RF clock for the FPGA was not detected, cannot upload waveforms without an RF clock present"
)
if (adc0):
raise RuntimeError(
"Error, the ADC RF clock for the FPGA was not detected, cannot read out ADC"
)
#Load the board with the channels
if (self.board_obj.configure_all_channels()):
raise RuntimeError(
"Error, could not configure channels for DAC test")
for i in range(0, adc_avgs):
if (self.board_obj.trigger()):
raise RuntimeError("Error triggering board")
else:
print("Trigger #" + str(i))
#Read out the adc
adc_samples = self.board_obj.readout_adc(self.adc_channel_num)
return adc_samples
c.post_delay = post_delay
c.waveform_amp_factor = amp_mul_factor
c.num_repeat_cycles = num_repeat_cycles
c.pre_delay = zero_delay
#Check the new parameters
c.check_parameters()
#Re-generate the channel data with the new values
c.generate_channel_data()
break
#If we just need to add a new channel
if (found == 0):
print("Creating new configuration for channel " + str(channel_number + 1))
c = rbd.rfsoc_channel("DAC", channel_number, locking_phase,
locking_amp_factor, zero_delay, post_delay,
waveform_period, num_repeat_cycles, amp_mul_factor,
waveform_filename, locking_filename, 0, 0)
board.channel_list.append(c)
#Save the board object to disk
rbd.save_rfsoc_board(board)
print("\n===================================\nSuccessfully added channel #" +
str(channel_number + 1))
print("Waveform file: " + waveform_filename + "\nPeriod: " +
str(waveform_period) + " (ns)\nWaveform amplitude multiplier: " +
str(amp_mul_factor) + "\nNumber of playback cycles: " +
str(num_repeat_cycles) + "\nDelay before experiment: " +
str(zero_delay) + " (ns)\nDelay after experiment: " + str(post_delay) +
" (ns)\nIs locking channel: " + ("YES" if is_locking == 1 else "NO") +