def parallella_serdes(
clock,
# porcupine board breakout
serial_tx_p,
serial_tx_n,
serial_rx_p,
serial_rx_n,
led,
reset=None):
"""
"""
assert len(led) == 8
nbanks = len(serial_tx_p)
assert (len(serial_tx_p) == len(serial_tx_n) == len(serial_rx_p) ==
len(serial_rx_n))
glbl = Global(clock, reset)
# signal interface to the prbs generate / check
locked = [Signal(bool(0)) for _ in range(nbanks)]
inject_error = [Signal(bool(0)) for _ in range(nbanks)]
word_count = [Signal(intbv(0)[64:]) for _ in range(nbanks)]
error_count = [Signal(intbv(0)[64:]) for _ in range(nbanks)]
prbsi = [Signal(intbv(0)[1:]) for _ in range(nbanks)]
prbso = [Signal(intbv(0)[1:]) for _ in range(nbanks)]
# diff buffers for the diff signals
obuf = output_diff_buffer(prbso, serial_tx_p, serial_tx_n)
ibuf = input_diff_buffer(serial_rx_p, serial_rx_n, prbsi)
insts = []
for bank in range(nbanks):
gg = prbs_generate(glbl, prbso[bank], inject_error[bank], order=23)
gc = prbs_check(glbl,
prbsi[bank],
locked[bank],
word_count[bank],
error_count[bank],
order=23)
for gg in (
gg,
gc,
):
insts.append(gg)
locks = ConcatSignal(*reversed(locked))
@always_comb
def led_assign():
led.next = concat("1010", locks[4:])
return ibuf, obuf, insts, led_assign
def parallella_serdes(
clock,
# porcupine board breakout
serial_tx_p, serial_tx_n,
serial_rx_p, serial_rx_n,
led, reset=None
):
"""
"""
assert len(led) == 8
nbanks = len(serial_tx_p)
assert (len(serial_tx_p) == len(serial_tx_n) ==
len(serial_rx_p) == len(serial_rx_n) )
glbl = Global(clock, reset)
# signal interface to the prbs generate / check
locked = [Signal(bool(0)) for _ in range(nbanks)]
inject_error = [Signal(bool(0)) for _ in range(nbanks)]
word_count = [Signal(intbv(0)[64:]) for _ in range(nbanks)]
error_count = [Signal(intbv(0)[64:]) for _ in range(nbanks)]
prbsi = [Signal(intbv(0)[1:]) for _ in range(nbanks)]
prbso = [Signal(intbv(0)[1:]) for _ in range(nbanks)]
# diff buffers for the diff signals
obuf_inst = output_diff_buffer(prbso, serial_tx_p, serial_tx_n)
ibuf_inst = input_diff_buffer(serial_rx_p, serial_rx_n, prbsi)
insts = []
for bank in range(nbanks):
gen_inst = prbs_generate(
glbl, prbso[bank], inject_error[bank],
order=23
)
insts += [gen_inst]
chk_inst = prbs_check(
glbl, prbsi[bank], locked[bank],
word_count[bank], error_count[bank],
order=23
)
insts += [chk_inst]
locks = ConcatSignal(*reversed(locked))
@always_comb
def led_assign():
led.next = concat("1010", locks[4:])
return myhdl.instances()
def _bench_prbs7():
tbdut = prbs_generate(glbl, prbs, order=7, initval=0x7F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# there is one zero at the beginning
yield clock.posedge
for ii, ep in enumerate(expected_pattern):
yield clock.posedge
assert prbs == ep
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
def bench_prbs7():
tbdut = prbs_generate(glbl, prbs, order=7, initval=0x7F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# there is one zero at the beginning
yield clock.posedge
for ii, ep in enumerate(expected_pattern):
yield clock.posedge
assert prbs == ep
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# convert the generator
inst = prbs_generate(glbl, prbs, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
inst = prbs_check(glbl, prbs, locked, word_count, error_count, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
def test_conversion(args=None):
args = tb_default_args(args)
clock = Clock(0, frequency=125e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
prbs = Signal(intbv(0)[8:])
# convert the generator
inst = prbs_generate(glbl, prbs, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
# convert the checker
locked = Signal(bool(0))
word_count = Signal(intbv(0)[64:])
error_count = Signal(intbv(0)[64:])
inst = prbs_check(glbl, prbs, locked, word_count, error_count, order=23)
inst.convert(hdl='Verilog', testbench=False, directory='output')
def _bench_prbs():
# currently only order 7, 9, 11, 15, 23, and 31 are coded in
# prbs feedback tap table, limit testing to one of these patterns
tbdut = prbs_generate(glbl, prbs, order=23)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# this test doesn't check the output (bad) simply checks that
# the module doesn't choke on the various word-lengths
for ii in range(27):
yield clock.posedge
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
def bench_prbs():
# currently only order 7, 9, 11, 15, 23, and 31 are coded in
# prbs feedback tap table, limit testing to one of these patterns
tbdut = prbs_generate(glbl, prbs, order=23)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
# this test doesn't check the output (bad) simply checks that
# the module doesn't choke on the various word-lengths
for ii in range(27):
yield clock.posedge
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
def _bench_prbs5():
tbdut = prbs_generate(glbl, prbs, order=5, initval=0x1F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
for ii, ep in enumerate(expected_pattern):
assert prbs == ep
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
def bench_prbs5():
tbdut = prbs_generate(glbl, prbs, order=5, initval=0x1F)
tbclk = clock.gen(hticks=8000)
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
for ii, ep in enumerate(expected_pattern):
assert prbs == ep
yield clock.posedge
# for debugging, test prints occur after the module prints
yield delay(1)
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
def _bench_prbs_checker():
tbgen = prbs_generate(glbl,
prbs,
inject_error=inject_error,
order=order)
tbdut = prbs_check(glbl,
prbs,
locked,
word_count,
error_count,
order=order)
tbclk = clock.gen()
maxcycles = 2 * ((2**order) - 1)
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
assert not locked
for ii in range(maxcycles):
yield clock.posedge
assert locked
assert error_count == 0
for ii in range(randint(0, 1000)):
yield clock.posedge
assert locked
assert error_count == 0
assert word_count > 0
lwc = int(word_count)
inject_error.next = True
yield clock.posedge
inject_error.next = False
yield clock.posedge
assert locked
for ii in range(randint(0, 1000)):
yield clock.posedge
assert locked
assert error_count == 1
assert word_count > lwc
lec = int(error_count)
inject_error.next = True
yield clock.posedge
yield clock.posedge
for ii in range(2000):
yield clock.posedge
if not locked:
break
assert error_count > lec
lec = int(error_count)
assert not locked
inject_error.next = False
for ii in range(maxcycles):
yield clock.posedge
assert locked
yield delay(100)
raise StopSimulation
return tbgen, tbdut, tbclk, tbstim
def bench_prbs_checker():
tbgen = prbs_generate(glbl, prbs, inject_error=inject_error,
order=order)
tbdut = prbs_check(glbl, prbs, locked, word_count,
error_count, order=order)
tbclk = clock.gen()
maxcycles = 2 * ((2**order)-1)
@instance
def tbstim():
yield reset.pulse(32)
yield clock.posedge
assert not locked
for ii in range(maxcycles):
yield clock.posedge
assert locked
assert error_count == 0
for ii in range(randint(0, 1000)):
yield clock.posedge
assert locked
assert error_count == 0
assert word_count > 0
lwc = int(word_count)
inject_error.next = True
yield clock.posedge
inject_error.next = False
yield clock.posedge
assert locked
for ii in range(randint(0, 1000)):
yield clock.posedge
assert locked
assert error_count == 1
assert word_count > lwc
lec = int(error_count)
inject_error.next = True
yield clock.posedge
yield clock.posedge
for ii in range(2000):
yield clock.posedge
if not locked:
break
assert error_count > lec
lec = int(error_count)
assert not locked
inject_error.next = False
for ii in range(maxcycles):
yield clock.posedge
assert locked
yield delay(100)
raise StopSimulation
return tbgen, tbdut, tbclk, tbstim
