def xula_vga(
# ~~~[PORTS]~~~
vselect,
hsync, vsync,
red, green, blue,
pxlen, active,
clock,
reset=None,
# ~~~~[PARAMETERS]~~~~
# @todo: replace these parameters with a single VGATimingParameter
resolution=(640, 480,),
color_depth=(8, 8, 8,),
refresh_rate=60,
line_rate=31250
):
"""
(arguments == ports)
Arguments:
vselect:
Parameters:
resolution: the video resolution
color_depth: the color depth of a pixel, the number of bits
for each color component in a pixel.
refresh_rate: the refresh rate of the video
"""
# stub out reset if needed
if reset is None:
reset = ResetSignal(0, active=0, async=False)
@always(clock.posedge)
def reset_stub():
reset.next = not reset.active
else:
reset_stub = None
# create the system-level signals, overwrite clock, reset
glbl = Global(clock=clock, reset=reset)
# VGA inteface
vga = VGA()
# assign the top-level ports to the VGA interface
vga.assign(
hsync=hsync, vsync=vsync,
red=red, green=green, blue=blue,
pxlen=pxlen, active=active
)
# video memory interface
vmem = VideoMemory(color_depth=color_depth)
# color bar generation
bar_inst = color_bars(glbl, vmem, resolution=resolution)
# VGA driver
vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution)
return myhdl.instances()
def mm_lt24lcdsys(clock, reset,
lcd_on, lcd_resetn, lcd_csn, lcd_rs,
lcd_wrn, lcd_rdn, lcd_data):
"""
"""
# interfaces
glbl = Global(clock, reset)
lcd = LT24Interface()
resolution = lcd.resolution
color_depth = lcd.color_depth
refresh_rate = 60
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
# assign the ports to the interface
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data)
# simulation mode, reduce the dead time between real-world ticks
# modules
gtck = glbl_timer_ticks(glbl, user_timer=16, tick_div=100)
gbar = color_bars(glbl, vmem, resolution=resolution,
color_depth=color_depth)
glcd = lt24lcd(glbl, vmem, lcd)
return gtck, gbar, glcd
def mm_lt24lcdsys(clock, reset, lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data):
"""
"""
# interfaces
glbl = Global(clock, reset)
lcd = LT24Interface()
resolution = lcd.resolution
color_depth = lcd.color_depth
refresh_rate = 60
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
# assign the ports to the interface
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
# simulation mode, reduce the dead time between real-world ticks
# modules
tck_inst = glbl_timer_ticks(glbl, user_timer=16, tick_div=100)
bar_inst = color_bars(glbl,
vmem,
resolution=resolution,
color_depth=color_depth)
lcd_inst = lt24lcd(glbl, vmem, lcd)
return myhdl.instances()
def mm_vgasys(
# ~~~[PORTS]~~~
clock,
reset,
vselect,
hsync,
vsync,
red,
green,
blue,
pxlen,
active,
# ~~~~[PARAMETERS]~~~~
resolution=(640, 480),
color_depth=(8, 8, 8),
refresh_rate=60,
line_rate=31250,
):
# create the system-level signals, overwrite clock, reset
glbl = Global(clock=clock, reset=reset)
# VGA interface
vga = VGA()
vga.assign(hsync=hsync, vsync=vsync, red=red, green=green, blue=blue, pxlen=pxlen, active=active)
# video memory interface
vmem = VideoMemory(color_depth=color_depth)
# instances of modules
bar_inst = color_bars(glbl, vmem, resolution=resolution, color_depth=color_depth)
vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution, refresh_rate=refresh_rate, line_rate=line_rate)
return myhdl.instances()
def mm_vgasys(
# ~~~[PORTS]~~~
clock,
reset,
vselect,
hsync,
vsync,
red,
green,
blue,
pxlen,
active,
# ~~~~[PARAMETERS]~~~~
resolution=(
640,
480,
),
color_depth=(
8,
8,
8,
),
refresh_rate=60,
line_rate=31250):
# create the system-level signals, overwrite clock, reset
glbl = Global(clock=clock, reset=reset)
# VGA interface
vga = VGA()
vga.assign(hsync=hsync,
vsync=vsync,
red=red,
green=green,
blue=blue,
pxlen=pxlen,
active=active)
# video memory interface
vmem = VideoMemory(color_depth=color_depth)
# instances of modules
bar_inst = color_bars(glbl,
vmem,
resolution=resolution,
color_depth=color_depth)
vga_inst = vga_sync(glbl,
vga,
vmem,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate)
return myhdl.instances()
def de0nano_lt24lcd(
clock,
reset,
led,
# LT24 LCD display signals
lcd_on,
lcd_resetn,
lcd_csn,
lcd_rs,
lcd_wrn,
lcd_rdn,
lcd_data,
):
"""
The port names are the same as those in the board definition
(names in the user manual) for automatic mapping by the
rhea.build automation.
"""
# signals and interfaces
glbl = Global(clock, reset)
# ----------------------------------------------------------------
# global ticks
gtick = glbl_timer_ticks(glbl, include_seconds=True, user_timer=16)
heartbeat = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def rtl_leds():
if glbl.tick_sec:
heartbeat.next = not heartbeat
led.next = concat(intbv(0)[7:], heartbeat)
# ----------------------------------------------------------------
# LCD dislay
lcd = LT24Interface()
resolution, color_depth = lcd.resolution, lcd.color_depth
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
# color bars and the interface between video source-n-sink
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
gbar = color_bars(glbl, vmem, resolution=resolution, color_depth=color_depth)
# LCD video driver
glcd = lt24lcd(glbl, vmem, lcd)
gens = gtick, rtl_leds, gbar, glcd
return gens
def de0nano_lt24lcd(clock, reset, led,
# LT24 LCD display signals
lcd_on, lcd_resetn, lcd_csn, lcd_rs,
lcd_wrn, lcd_rdn, lcd_data
):
"""
The port names are the same as those in the board definition
(names in the user manual) for automatic mapping by the
rhea.build automation.
"""
# signals and interfaces
glbl = Global(clock, reset)
# ----------------------------------------------------------------
# global ticks
gtick = glbl_timer_ticks(glbl, include_seconds=True,
user_timer=16)
heartbeat = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def rtl_leds():
if glbl.tick_sec:
heartbeat.next = not heartbeat
led.next = concat(intbv(0)[7:], heartbeat)
# ----------------------------------------------------------------
# LCD dislay
lcd = LT24Interface()
resolution, color_depth = lcd.resolution, lcd.color_depth
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data)
# color bars and the interface between video source-n-sink
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
gbar = color_bars(glbl, vmem, resolution=resolution,
color_depth=color_depth)
# LCD video driver
glcd = lt24lcd(glbl, vmem, lcd)
gens = gtick, rtl_leds, gbar, glcd
return gens
def xula_vga(
# ~~~[PORTS]~~~
clock, reset, vselect,
hsync, vsync,
red, green, blue,
pxlen, active,
# ~~~~[PARAMETERS]~~~~
resolution=(640, 480,),
color_depth=(10, 10, 10,),
refresh_rate=60,
line_rate=31250
):
"""
"""
# create the system-level signals, overwrite clock, reset
glbl = Global(clock=clock, reset=reset)
# VGA inteface
vga = VGA()
vga.assign(
hsync=hsync, vsync=vsync,
red=red, green=green, blue=blue,
pxlen=pxlen, active=active
)
# video memory interface
vmem = VideoMemory()
# color bar generation
bar_inst = color_bars(glbl, vmem, resolution=resolution)
# VGA driver
vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution)
return myhdl.instances()
def de0nano_converters(
clock,
reset,
led,
# ADC signals
adc_cs_n,
adc_saddr,
adc_sdat,
adc_sclk,
# Accelerometer and I2C signals
i2c_sclk,
i2c_sdat,
g_sensor_cs_n,
g_sensor_int,
# LT24 LCD display signals
lcd_on,
lcd_resetn,
lcd_csn,
lcd_rs,
lcd_wrn,
lcd_rdn,
lcd_data):
"""
The port names are the same as those in the board definition
(names in the user manual) for automatic mapping by the
rhea.build automation.
"""
# signals and interfaces
glbl = Global(clock, reset)
adcbus = SPIBus()
adcbus.mosi, adcbus.miso, adcbus.csn, adcbus.sck = (adc_saddr, adc_sdat,
adc_cs_n, adc_sclk)
fifobus = FIFOBus(width=16, size=16)
channel = Signal(intbv(0, min=0, max=8))
# ----------------------------------------------------------------
# global ticks
gtick = glbl_timer_ticks(glbl, include_seconds=True, user_timer=16)
# ----------------------------------------------------------------
# instantiate the ADC controller (retieves samples)
gconv = adc128s022(glbl, fifobus, adcbus, channel)
# read the samples out of the FIFO interface
fiford = Signal(bool(0))
@always(clock.posedge)
def rtl_read():
fiford = not fifobus.empty
@always_comb
def rtl_read_gate():
fifobus.rd.next = fiford and not fifobus.empty
# for now assign the samples to the LEDs for viewing
heartbeat = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def rtl_leds():
if glbl.tick_sec:
heartbeat.next = not heartbeat
led.next = concat(fifobus.rdata[12:5], heartbeat)
# ----------------------------------------------------------------
# LCD dislay
lcd = LT24Interface()
resolution, color_depth = lcd.resolution, lcd.color_depth
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn, lcd_rdn, lcd_data)
# color bars and the interface between video source-n-sink
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
gbar = color_bars(glbl,
vmem,
resolution=resolution,
color_depth=color_depth)
# LCD video driver
glcd = lt24lcd(glbl, vmem, lcd)
gens = gtick, gconv, rtl_read, rtl_leds, gbar, glcd
return gens
def de0nano_converters(clock, reset, led,
# ADC signals
adc_cs_n, adc_saddr, adc_sdat, adc_sclk,
# Accelerometer and I2C signals
i2c_sclk, i2c_sdat, g_sensor_cs_n, g_sensor_int,
# LT24 LCD display signals
lcd_on, lcd_resetn, lcd_csn, lcd_rs,
lcd_wrn, lcd_rdn, lcd_data
):
"""
The port names are the same as those in the board definition
(names in the user manual) for automatic mapping by the
rhea.build automation.
"""
# signals and interfaces
glbl = Global(clock, reset)
adcbus = SPIBus()
adcbus.mosi, adcbus.miso, adcbus.csn, adcbus.sck = (
adc_saddr, adc_sdat, adc_cs_n, adc_sclk)
fifobus = FIFOBus(width=16, size=16)
channel = Signal(intbv(0, min=0, max=8))
# ----------------------------------------------------------------
# global ticks
gtick = glbl_timer_ticks(glbl, include_seconds=True,
user_timer=16)
# ----------------------------------------------------------------
# instantiate the ADC controller (retieves samples)
gconv = adc128s022(glbl, fifobus, adcbus, channel)
# read the samples out of the FIFO interface
fiford = Signal(bool(0))
@always(clock.posedge)
def rtl_read():
fiford = not fifobus.empty
@always_comb
def rtl_read_gate():
fifobus.rd.next = fiford and not fifobus.empty
# for now assign the samples to the LEDs for viewing
heartbeat = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def rtl_leds():
if glbl.tick_sec:
heartbeat.next = not heartbeat
led.next = concat(fifobus.rdata[12:5], heartbeat)
# ----------------------------------------------------------------
# LCD dislay
lcd = LT24Interface()
resolution, color_depth = lcd.resolution, lcd.color_depth
lcd.assign(lcd_on, lcd_resetn, lcd_csn, lcd_rs, lcd_wrn,
lcd_rdn, lcd_data)
# color bars and the interface between video source-n-sink
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
gbar = color_bars(glbl, vmem, resolution=resolution,
color_depth=color_depth)
# LCD video driver
glcd = lt24lcd(glbl, vmem, lcd)
gens = gtick, gconv, rtl_read, rtl_leds, gbar, glcd
return gens
def zybo_vga(
# Ports
led,
btn,
vga_red,
vga_grn,
vga_blu,
vga_hsync,
vga_vsync,
clock,
reset=None,
# Parameters
resolution=(1280, 1024),
color_depth=(5, 6, 5),
refresh_rate=60,
line_rate=64512):
"""
This is a VGA example for the Digilent Zybo board.
Arguments (ports):
led: the Zybo 4 LEDs
btn: the Zybo 4 buttons
vga_red: red bits
vga_grn: green bits
vga_blu: blue bits
vga_hsync: horizontal sync
vga_vsync: vertical sync
Parameters:
resolution: the monitor desired resolution
color_depth: the number of bits per color
refresh_rate: the monitor refresh rate
line_rate: the monitor line rate
Common configurations
600x480, 60
800x600, 60, 37880
1280x1024, 60, 64512
"""
glbl = Global(clock=clock, reset=reset)
# VGA interface
vga = VGA(color_depth=color_depth)
vga.assign(
hsync=vga_hsync,
vsync=vga_vsync,
red=vga_red,
green=vga_grn,
blue=vga_blu,
)
# video memory interface
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
# rhea.core instances
bar_inst = color_bars(glbl,
vmem,
resolution=resolution,
color_depth=color_depth)
vga_inst = vga_sync(glbl,
vga,
vmem,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate)
bcnt = Signal(intbv(0, min=0, max=clock.frequency))
blink = Signal(bool(0))
nticks = int(clock.frequency - 1)
@always(clock.posedge)
def beh_blink():
if bcnt == nticks:
bcnt.next = 0
blink.next = not blink
else:
bcnt.next = bcnt + 1
@always(clock.posedge)
def beh_led():
led.next = concat("000", blink)
return bar_inst, vga_inst, beh_blink, beh_led
def zybo_vga(
# Ports
led, btn, vga_red, vga_grn, vga_blu,
vga_hsync, vga_vsync, clock, reset=None,
# Parameters
resolution=(1280, 1024), color_depth=(5, 6, 5),
refresh_rate=60, line_rate=64512):
"""
This is a VGA example for the Digilent Zybo board.
Arguments (ports):
led: the Zybo 4 LEDs
btn: the Zybo 4 buttons
vga_red: red bits
vga_grn: green bits
vga_blu: blue bits
vga_hsync: horizontal sync
vga_vsync: vertical sync
Parameters:
resolution: the monitor desired resolution
color_depth: the number of bits per color
refresh_rate: the monitor refresh rate
line_rate: the monitor line rate
Common configurations
600x480, 60
800x600, 60, 37880
1280x1024, 60, 64512
"""
glbl = Global(clock=clock, reset=reset)
# VGA interface
vga = VGA(color_depth=color_depth)
vga.assign(hsync=vga_hsync, vsync=vga_vsync,
red=vga_red, green=vga_grn, blue=vga_blu,)
# video memory interface
vmem = VideoMemory(resolution=resolution, color_depth=color_depth)
# rhea.core instances
bar_inst = color_bars(glbl, vmem, resolution=resolution,
color_depth=color_depth)
vga_inst = vga_sync(glbl, vga, vmem, resolution=resolution,
refresh_rate=refresh_rate, line_rate=line_rate)
bcnt = Signal(intbv(0, min=0, max=clock.frequency))
blink = Signal(bool(0))
nticks = int(clock.frequency-1)
@always(clock.posedge)
def beh_blink():
if bcnt == nticks:
bcnt.next = 0
blink.next = not blink
else:
bcnt.next = bcnt + 1
@always(clock.posedge)
def beh_led():
led.next = concat("000", blink)
return bar_inst, vga_inst, beh_blink, beh_led
