def convert(args=None):
wclk = Signal(bool(0))
datain = Signal(intbv(0)[36:])
src_rdy_i = Signal(bool(0))
dst_rdy_o = Signal(bool(0))
space = Signal(intbv(0)[16:])
rclk = Signal(bool(0))
dataout = Signal(intbv(0)[36:])
src_rdy_o = Signal(bool(0))
dst_rdy_i = Signal(bool(0))
occupied = Signal(intbv(0)[16:])
reset = ResetSignal(0, active=1, async=True)
inst = fifo_2clock_cascade(
wclk, datain, src_rdy_i, dst_rdy_o, space,
rclk, dataout, src_rdy_o, dst_rdy_i, occupied,
reset
)
tb_convert(inst)
clock = Signal(bool(0))
clear = Signal(bool(0))
inst = fifo_short(
clock, reset, clear,
datain, src_rdy_i, dst_rdy_o,
dataout, src_rdy_o, dst_rdy_i
)
tb_convert(inst)
def convert():
"""convert the faux-top-level"""
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
sck, mosi, miso, ss = Signals(bool(0), 4)
inst = spi_controller_top(clock, reset, sck, mosi, miso, ss)
tb_convert(inst)
def convert():
"""convert the faux-top-level"""
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, isasync=False)
sck, mosi, miso, ss = Signals(bool(0), 4)
inst = spi_controller_top(clock, reset, sck, mosi, miso, ss)
tb_convert(inst)
def convert(args=None):
wclk = Signal(bool(0))
datain = Signal(intbv(0)[36:])
src_rdy_i = Signal(bool(0))
dst_rdy_o = Signal(bool(0))
space = Signal(intbv(0)[16:])
rclk = Signal(bool(0))
dataout = Signal(intbv(0)[36:])
src_rdy_o = Signal(bool(0))
dst_rdy_i = Signal(bool(0))
occupied = Signal(intbv(0)[16:])
reset = ResetSignal(0, active=1, isasync=True)
inst = fifo_2clock_cascade(
wclk, datain, src_rdy_i, dst_rdy_o, space,
rclk, dataout, src_rdy_o, dst_rdy_i, occupied,
reset
)
tb_convert(inst)
clock = Signal(bool(0))
clear = Signal(bool(0))
inst = fifo_short(
clock, reset, clear,
datain, src_rdy_i, dst_rdy_o,
dataout, src_rdy_o, dst_rdy_i
)
tb_convert(inst)
def convert():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
sck = Signal(bool(0))
mosi = Signal(bool(0))
miso = Signal(bool(0))
ss = Signal(bool(0))
tb_convert(m_test_top, clock, reset, sck, mosi, miso, ss)
def convert():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
sck = Signal(bool(0))
mosi = Signal(bool(0))
miso = Signal(bool(0))
ss = Signal(bool(0))
tb_convert(m_test_top, clock, reset, sck, mosi, miso, ss)
def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
glbl = Global(clock, None)
led = Signal(intbv(0)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uart_dtr = Signal(bool(0))
uart_rts = Signal(bool(0))
uartmdl = UARTModel()
@myhdl.block
def bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = icestick_blinky_host(clock, led, pmod,
uart_tx, uart_rx,
uart_dtr, uart_rts)
@instance
def tbstim():
yield delay(1000)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = int((1/115200.) / 1e-9) * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(bench_ibh, args=args)
inst = icestick_blinky_host(
clock, led, pmod,
uart_tx, uart_rx, uart_dtr, uart_rts
)
tb_convert(inst)
def testbench_streamer(args=None):
args = tb_default_args(args)
if not hasattr(args, 'keep'):
args.keep = False
if not hasattr(args, 'bustype'):
args.bustype = 'barebone'
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
# @todo: support all stream types ...
upstream = AXI4StreamLitePort(data_width=32)
downstream = AXI4StreamLitePort(data_width=32)
@myhdl.block
def bench_streamer():
tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
tbclk = clock.gen()
dataout = []
@instance
def tbstim():
yield reset.pulse(42)
downstream.awaccept.next = True
downstream.waccept.next = True
data = [randint(0, (2**32)-1) for _ in range(10)]
for dd in data:
upstream.awvalid.next = True
upstream.awdata.next = 0xA
upstream.wvalid.next = True
upstream.wdata.next = dd
yield clock.posedge
upstream.awvalid.next = False
upstream.wvalid.next = False
# @todo: wait the appropriate delay given the number of
# @todo: streaming registers
yield delay(100)
print(data)
print(dataout)
assert False not in [di == do for di, do in zip(data, dataout)]
raise StopSimulation
@always(clock.posedge)
def tbcap():
if downstream.wvalid:
dataout.append(int(downstream.wdata))
return tbdut, tbclk, tbstim, tbcap
run_testbench(bench_streamer, args=args)
inst = streamer_top(clock, reset, upstream, downstream)
tb_convert(inst)
def testbench_streamer(args=None):
args = tb_default_args(args)
if not hasattr(args, 'keep'):
args.keep = False
if not hasattr(args, 'bustype'):
args.bustype = 'barebone'
clock = Clock(0, frequency=100e6)
reset = Reset(0, active=1, isasync=False)
glbl = Global(clock, reset)
# @todo: support all stream types ...
upstream = AXI4StreamLitePort(data_width=32)
downstream = AXI4StreamLitePort(data_width=32)
@myhdl.block
def bench_streamer():
tbdut = streamer_top(clock, reset, upstream, downstream, keep=args.keep)
tbclk = clock.gen()
dataout = []
@instance
def tbstim():
yield reset.pulse(42)
downstream.awaccept.next = True
downstream.waccept.next = True
data = [randint(0, (2**32)-1) for _ in range(10)]
for dd in data:
upstream.awvalid.next = True
upstream.awdata.next = 0xA
upstream.wvalid.next = True
upstream.wdata.next = dd
yield clock.posedge
upstream.awvalid.next = False
upstream.wvalid.next = False
# @todo: wait the appropriate delay given the number of
# @todo: streaming registers
yield delay(100)
print(data)
print(dataout)
assert False not in [di == do for di, do in zip(data, dataout)]
raise StopSimulation
@always(clock.posedge)
def tbcap():
if downstream.wvalid:
dataout.append(int(downstream.wdata))
return tbdut, tbclk, tbstim, tbcap
run_testbench(bench_streamer, args=args)
inst = streamer_top(clock, reset, upstream, downstream)
tb_convert(inst)
def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
glbl = Global(clock, None)
led = Signal(intbv(0)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uart_dtr = Signal(bool(0))
uart_rts = Signal(bool(0))
uartmdl = UARTModel()
@myhdl.block
def bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = icestick_blinky_host(clock, led, pmod, uart_tx, uart_rx, uart_dtr, uart_rts)
@instance
def tbstim():
yield delay(1000)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = int((1 / 115200.0) / 1e-9) * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise TimeoutError
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(bench_ibh, args=args)
inst = icestick_blinky_host(clock, led, pmod, uart_tx, uart_rx, uart_dtr, uart_rts)
tb_convert(inst)
def test_xula_vga(args=None):
args = tb_default_args(args)
resolution = (64, 48,)
refresh_rate = 60
line_rate = 31250
color_depth = (3, 4, 3,)
clock = Clock(0, frequency=12e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
vga = VGA(color_depth=color_depth)
vga_hsync, vga_vsync = Signals(bool(0), 2)
vga_red, vga_green, vga_blue = Signals(intbv(0)[6:], 3)
vselect = Signal(bool(0))
pxlen, active = Signals(bool(0), 2)
@myhdl.block
def bench():
tbdut = xula_vga(
clock, reset,
vselect, vga_hsync, vga_vsync,
vga_red, vga_green, vga_blue,
pxlen, active,
resolution=resolution, color_depth=color_depth,
refresh_rate=refresh_rate, line_rate=line_rate
)
tbclk = clock.gen()
mdl = VGADisplay(frequency=clock.frequency,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate,
color_depth=color_depth)
tbmdl = mdl.process(glbl, vga)
@instance
def tbstim():
yield delay(100000)
raise StopSimulation
return tbdut, tbclk, tbmdl, tbstim
# run the above stimulus, the above is not self checking it simply
# verifies the code will simulate.
run_testbench(bench, args=args)
portmap = dict(vselect=vselect, hsync=vga_hsync, vsync=vga_vsync,
red=vga_red, green=vga_green, blue=vga_blue,
clock=clock)
# convert the module, check for any conversion errors
tb_convert(xula_vga, **portmap)
def convert():
FDO = Signal(intbv(0)[8:])
FDI = Signal(intbv(0)[8:])
FDS = Signal(bool(0))
SLWR, SLRD, SLOE = [Signal(bool(0)) for _ in range(3)]
FLAGA, FLAGB, FLAGC, FLAGD = [Signal(bool(0)) for _ in range(4)]
ADDR = Signal(intbv(0)[2:])
IFCLK = Signal(bool(0))
RST = ResetSignal(bool(1), active=0, isasync=True)
LEDS = Signal(intbv(0)[8:])
PKTEND = Signal(bool(0))
inst = fpgalink_nexys(IFCLK, RST, SLWR, SLRD, SLOE, FDI, FDO, FDS, ADDR,
FLAGA, FLAGB, FLAGC, FLAGD, PKTEND, LEDS)
tb_convert(inst)
def convert():
FDO = Signal(intbv(0)[8:])
FDI = Signal(intbv(0)[8:])
FDS = Signal(bool(0))
SLWR,SLRD,SLOE = [Signal(bool(0)) for _ in range(3)]
FLAGA,FLAGB,FLAGC,FLAGD = [Signal(bool(0)) for _ in range(4)]
ADDR = Signal(intbv(0)[2:])
IFCLK = Signal(bool(0))
RST = ResetSignal(bool(1), active=0, async=True)
LEDS = Signal(intbv(0)[8:])
PKTEND = Signal(bool(0))
inst = fpgalink_nexys(
IFCLK, RST, SLWR, SLRD, SLOE, FDI, FDO,
FDS, ADDR, FLAGA, FLAGB, FLAGC, FLAGD, PKTEND, LEDS
)
tb_convert(inst)
def test_conversion():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
sdi, sdo = Signals(bool(0), 2)
# a top-level conversion stub
@myhdl.block
def top_stub(clock, reset, sdi, sdo):
pin = [Signal(intbv(0)[16:0]) for _ in range(1)]
pout = [Signal(intbv(0)[16:0]) for _ in range(3)]
valid = Signal(bool(0))
stub_inst = io_stub(clock, reset, sdi, sdo, pin, pout, valid)
return stub_inst
# convert the design stub
inst = top_stub(clock, reset, sdi, sdo)
tb_convert(inst)
def test_conversion():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, isasync=False)
sdi, sdo = Signals(bool(0), 2)
# a top-level conversion stub
@myhdl.block
def top_stub(clock, reset, sdi, sdo):
pin = [Signal(intbv(0)[16:0]) for _ in range(1)]
pout = [Signal(intbv(0)[16:0]) for _ in range(3)]
valid = Signal(bool(0))
stub_inst = io_stub(clock, reset, sdi, sdo, pin, pout, valid)
return stub_inst
# convert the design stub
inst = top_stub(clock, reset, sdi, sdo)
tb_convert(inst)
def test_zybo_vga(args=None):
args = tb_default_args(args)
resolution = (80, 60,)
refresh_rate = 60
line_rate = 31250
color_depth = (6, 6, 6,)
clock = Clock(0, frequency=125e6)
glbl = Global(clock)
vga = VGA(color_depth=color_depth)
vga_hsync, vga_vsync = Signals(bool(0), 2)
vga_red, vga_green, vga_blue = Signals(intbv(0)[6:], 3)
led, btn = Signals(intbv(0)[4:], 2)
@myhdl.block
def bench():
tbdut = zybo_vga(led, btn, vga_red, vga_green, vga_blue,
vga_hsync, vga_vsync, clock,
resolution=resolution, color_depth=color_depth,
refresh_rate=refresh_rate, line_rate=line_rate)
tbclk = clock.gen()
mdl = VGADisplay(frequency=clock.frequency, resolution=resolution,
refresh_rate=refresh_rate, line_rate=line_rate,
color_depth=color_depth)
tbmdl = mdl.process(glbl, vga)
@instance
def tbstim():
yield delay(100000)
raise StopSimulation
return tbdut, tbclk, tbmdl, tbstim
# run the above testbench, the above testbench doesn't functionally
# verify anything only verifies basics.
run_testbench(bench, args=args)
# test conversion
portmap = dict(led=led, btn=btn, vga_red=vga_red, vga_grn=vga_green,
vga_blu=vga_blue, vga_hsync=vga_hsync, vga_vsync=vga_vsync,
clock=clock)
inst = zybo_vga(**portmap)
tb_convert(inst)
def convert(color_depth=(10, 10, 10,)):
""" convert the vgasys to verilog
"""
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
vselect = Signal(bool(0))
hsync = Signal(bool(0))
vsync = Signal(bool(0))
cd = color_depth
red = Signal(intbv(0)[cd[0]:])
green = Signal(intbv(0)[cd[1]:])
blue = Signal(intbv(0)[cd[2]:])
pxlen = Signal(bool(0))
active = Signal(bool(0))
inst = xula_vga(
clock, reset, vselect,
hsync, vsync, red, green, blue,
pxlen, active
)
tb_convert(inst)
def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
led = Signal(intbv(0)[8:])
sw = Signal(intbv(1)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uartmdl = UARTModel()
baudrate = uartmdl.baudrate
baudticks = int((1/baudrate) / 1e-9)
@myhdl.block
def bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = atlys_blinky_host(clock, reset, led, sw, pmod,
uart_tx, uart_rx)
@instance
def tbstim():
yield reset.pulse(33)
yield delay(1000)
# test loopback
for ii in range(5):
wb = randint(0, 255)
uartmdl.write(wb)
# wait for the send (return)
yield delay(baudticks*(8+2) + 2*baudticks)
rb = uartmdl.read()
assert rb == wb
sw.next = 0
yield delay(100)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = baudticks * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise Exception("TimeoutError")
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(bench_ibh, args=args)
inst = atlys_blinky_host(clock, reset, led, sw, pmod, uart_tx, uart_rx)
tb_convert(inst)
def test_xula_vga(args=None):
args = tb_default_args(args)
resolution = (64, 48)
refresh_rate = 60
line_rate = 31250
color_depth = (3, 4, 3)
clock = Clock(0, frequency=12e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
vga = VGA(color_depth=color_depth)
vga_hsync, vga_vsync = Signals(bool(0), 2)
vga_red, vga_green, vga_blue = Signals(intbv(0)[6:], 3)
vselect = Signal(bool(0))
pxlen, active = Signals(bool(0), 2)
@myhdl.block
def bench():
tbdut = xula_vga(
clock,
reset,
vselect,
vga_hsync,
vga_vsync,
vga_red,
vga_green,
vga_blue,
pxlen,
active,
resolution=resolution,
color_depth=color_depth,
refresh_rate=refresh_rate,
line_rate=line_rate,
)
tbclk = clock.gen()
mdl = VGADisplay(
frequency=clock.frequency,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate,
color_depth=color_depth,
)
tbmdl = mdl.process(glbl, vga)
@instance
def tbstim():
yield delay(100000)
raise StopSimulation
return tbdut, tbclk, tbmdl, tbstim
# run the above stimulus, the above is not self checking it simply
# verifies the code will simulate.
run_testbench(bench, args=args)
portmap = dict(
vselect=vselect, hsync=vga_hsync, vsync=vga_vsync, red=vga_red, green=vga_green, blue=vga_blue, clock=clock
)
# convert the module, check for any conversion errors
tb_convert(xula_vga, **portmap)
def test_zybo_vga(args=None):
args = tb_default_args(args)
resolution = (
80,
60,
)
refresh_rate = 60
line_rate = 31250
color_depth = (
6,
6,
6,
)
clock = Clock(0, frequency=125e6)
glbl = Global(clock)
vga = VGA(color_depth=color_depth)
vga_hsync, vga_vsync = Signals(bool(0), 2)
vga_red, vga_green, vga_blue = Signals(intbv(0)[6:], 3)
led, btn = Signals(intbv(0)[4:], 2)
@myhdl.block
def bench():
tbdut = zybo_vga(led,
btn,
vga_red,
vga_green,
vga_blue,
vga_hsync,
vga_vsync,
clock,
resolution=resolution,
color_depth=color_depth,
refresh_rate=refresh_rate,
line_rate=line_rate)
tbclk = clock.gen()
mdl = VGADisplay(frequency=clock.frequency,
resolution=resolution,
refresh_rate=refresh_rate,
line_rate=line_rate,
color_depth=color_depth)
tbmdl = mdl.process(glbl, vga)
@instance
def tbstim():
yield delay(100000)
raise StopSimulation
return tbdut, tbclk, tbmdl, tbstim
# run the above testbench, the above testbench doesn't functionally
# verify anything only verifies basics.
run_testbench(bench, args=args)
# test conversion
portmap = dict(led=led,
btn=btn,
vga_red=vga_red,
vga_grn=vga_green,
vga_blu=vga_blue,
vga_hsync=vga_hsync,
vga_vsync=vga_vsync,
clock=clock)
inst = zybo_vga(**portmap)
tb_convert(inst)
def test(args=None):
if args is None:
args = Namespace(trace=False)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
sdi, sdo = [Signal(bool(0)) for _ in range(2)]
pin = [Signal(intbv(0)[16:]) for _ in range(1)]
pout = [Signal(intbv(0)[16:]) for _ in range(3)]
valid = Signal(bool(0))
def bench_serio():
tbclk = clock.gen()
tbdut = io_stub(clock, reset, sdi, sdo, pin, pout, valid)
@instance
def tbstim():
yield reset.pulse(13)
yield clock.posedge
for pp in pout:
pp.next = 0
sdi.next = False
yield delay(200)
yield clock.posedge
for ii in range(1000):
yield clock.posedge
assert sdo == False
assert pin[0] == 0
for pp in pout:
pp.next = 0xFFFF
sdi.next = True
yield valid.posedge
yield delay(200)
yield clock.posedge
for ii in range(1000):
yield clock.posedge
assert sdo == True
assert pin[0] == 0xFFFF
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_serio, args=args)
# a top-level conversion stub
def top_stub(clock, reset, sdi, sdo):
pin = [Signal(intbv(0)[16:0]) for _ in range(1)]
pout = [Signal(intbv(0)[16:0]) for _ in range(3)]
valid = Signal(bool(0))
stub_inst = io_stub(clock, reset, sdi, sdo, pin, pout, valid)
return stub_inst
# convert the design stub
tb_convert(top_stub, clock, reset, sdi, sdo)
def test(args=None):
if args is None:
args = Namespace(trace=False)
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
sdi, sdo = [Signal(bool(0)) for _ in range(2)]
pin = [Signal(intbv(0)[16:]) for _ in range(1)]
pout = [Signal(intbv(0)[16:]) for _ in range(3)]
valid = Signal(bool(0))
def bench_serio():
tbclk = clock.gen()
tbdut = io_stub(clock, reset, sdi, sdo, pin, pout, valid)
@instance
def tbstim():
yield reset.pulse(13)
yield clock.posedge
for pp in pout:
pp.next = 0
sdi.next = False
yield delay(200)
yield clock.posedge
for ii in range(1000):
yield clock.posedge
assert sdo == False
assert pin[0] == 0
for pp in pout:
pp.next = 0xFFFF
sdi.next = True
yield valid.posedge
yield delay(200)
yield clock.posedge
for ii in range(1000):
yield clock.posedge
assert sdo == True
assert pin[0] == 0xFFFF
raise StopSimulation
return tbdut, tbclk, tbstim
run_testbench(bench_serio, args=args)
# a top-level conversion stub
def top_stub(clock, reset, sdi, sdo):
pin = [Signal(intbv(0)[16:0]) for _ in range(1)]
pout = [Signal(intbv(0)[16:0]) for _ in range(3)]
valid = Signal(bool(0))
stub_inst = io_stub(clock, reset, sdi, sdo, pin, pout, valid)
return stub_inst
# convert the design stub
tb_convert(top_stub, clock, reset, sdi, sdo)
def test_ibh(args=None):
args = tb_default_args(args)
numbytes = 13
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=True)
glbl = Global(clock, reset)
led = Signal(intbv(0)[8:])
sw = Signal(intbv(1)[8:])
pmod = Signal(intbv(0)[8:])
uart_tx = Signal(bool(0))
uart_rx = Signal(bool(0))
uartmdl = UARTModel()
baudrate = uartmdl.baudrate
baudticks = int((1 / baudrate) / 1e-9)
@myhdl.block
def bench_ibh():
tbclk = clock.gen()
tbmdl = uartmdl.process(glbl, uart_tx, uart_rx)
tbdut = atlys_blinky_host(clock, reset, led, sw, pmod, uart_tx,
uart_rx)
@instance
def tbstim():
yield reset.pulse(33)
yield delay(1000)
# test loopback
for ii in range(5):
wb = randint(0, 255)
uartmdl.write(wb)
# wait for the send (return)
yield delay(baudticks * (8 + 2) + 2 * baudticks)
rb = uartmdl.read()
assert rb == wb
sw.next = 0
yield delay(100)
# send a write that should enable all five LEDs
pkt = CommandPacket(False, address=0x20, vals=[0xFF])
for bb in pkt.rawbytes:
uartmdl.write(bb)
waitticks = baudticks * 10 * 28
yield delay(waitticks)
timeout = 100
yield delay(waitticks)
# get the response packet
for ii in range(PACKET_LENGTH):
rb = uartmdl.read()
while rb is None and timeout > 0:
yield clock.posedge
rb = uartmdl.read()
timeout -= 1
if rb is None:
raise Exception("TimeoutError")
# the last byte should be the byte written
assert rb == 0xFF
yield delay(1000)
raise StopSimulation
return tbclk, tbmdl, tbdut, tbstim
run_testbench(bench_ibh, args=args)
inst = atlys_blinky_host(clock, reset, led, sw, pmod, uart_tx, uart_rx)
tb_convert(inst)
def test_convert():
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
mon = Signal(intbv(0)[8:])
inst = peripheral_top(clock, reset, mon)
tb_convert(inst)
def test_convert():
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
mon = Signal(intbv(0)[8:])
inst = peripheral_top(clock, reset, mon)
tb_convert(inst)
