def compile_all_cores(cfg_dir, rtl_root, run_root, target='generic',
flow='vsim', stdout=None, stderr=None):
sim_cc, sim_exe = sim_utils.get_rtl_tools(flow)
for root, d, files in os.walk(cfg_dir):
for f in files:
if not f.endswith('.json'): continue
arch_cfg = os.path.join(root, f)
cfg = read_arch_config(arch_cfg)
tgt_root = os.path.join(rtl_root,'core',cfg.name,cfg.get_tgt_attr())
if not os.path.isdir(tgt_root): continue
arch_md5 = sys_utils.md5_file(arch_cfg)
rtl_path = (os.path.join(rtl_root, 'common'),
os.path.join(rtl_root, 'memory'),
os.path.join(rtl_root, 'top'), tgt_root)
t_wd = get_target_out_dir(cfg.get_tgt_sig(), arch_md5, run_root)
lib_path = os.path.join(t_wd, 'hw-libs')
solver_rtl_gen.generate_rtl_package(
cfg, lib_path, rtl_path=rtl_path,
tb_path = (os.path.join(rtl_root, 'testbench'),),
def_path = (os.path.join(rtl_root, 'define'),),
target=target, tb_module='simd_top_testbench', lib='work')
sim_wd = os.path.join(lib_path, '%s_wd'%flow)
# Check if it is necessary to compile the simulation libraries
check_and_compile_solver_rtl(lib_path, sim_wd, flow, sim_cc,
stdout=stdout, stderr=stderr)
def run_solver_bin_ar(bin_ar,
arch_config,
rtl_root,
run_root,
sim_out=None,
target='generic',
flow='vsim',
stdout=None,
stderr=None):
global VERBOSE
if not os.access(arch_config, os.R_OK):
raise RuntimeError('Invalid architecture config "%s"' % arch_config)
arch_md5 = sys_utils.md5_file(arch_config)
cfg = read_arch_config(arch_config)
tgt_sig = cfg.get_tgt_sig()
sim_cc, sim_exe = sim_utils.get_rtl_tools(flow)
sys_utils.mkdir_p(os.path.abspath(run_root))
t_wd = get_target_out_dir(cfg.get_tgt_sig(), arch_md5, run_root)
lib_path = os.path.join(t_wd, 'hw-libs')
# If RTL folder does not exist, generate it from config file
if not os.path.isdir(lib_path):
tgt_rtl_root = os.path.join(rtl_root, 'core', cfg.name,
cfg.get_tgt_attr())
rtl_path = (os.path.join(rtl_root,
'common'), os.path.join(rtl_root, 'memory'),
os.path.join(rtl_root, 'top'), tgt_rtl_root)
solver_rtl_gen.generate_rtl_package(
cfg,
lib_path,
rtl_path=rtl_path,
tb_path=(os.path.join(rtl_root, 'testbench'), ),
def_path=(os.path.join(rtl_root, 'define'), ),
target=target,
tb_module='simd_top_testbench',
lib='work')
sim_wd = os.path.join(lib_path, '%s_wd' % flow)
# Check if it is necessary to compile the simulation libraries
check_and_compile_solver_rtl(lib_path,
sim_wd,
flow,
sim_cc,
stdout=stdout,
stderr=stderr)
# Setup application files
clean_solver_rtl_simulation(sim_wd)
app_name = sys_utils.get_path_basename(bin_ar)
setup_solver_mem_files(bin_ar, sim_wd)
# Run the actual simulation
run_solver_rtl_simulation(sim_exe,
sim_wd,
flow,
lib_path,
cfg,
stdout=stdout,
stderr=stderr,
gui=False)
if not sim_out: sim_out = os.path.join(t_wd, 'sim-out', app_name)
move_dump_files(sim_wd, sim_out)
def compile_all_cores(cfg_dir,
rtl_root,
run_root,
target='generic',
flow='vsim',
stdout=None,
stderr=None):
sim_cc, sim_exe = sim_utils.get_rtl_tools(flow)
for root, d, files in os.walk(cfg_dir):
for f in files:
if not f.endswith('.json'): continue
arch_cfg = os.path.join(root, f)
cfg = read_arch_config(arch_cfg)
tgt_root = os.path.join(rtl_root, 'core', cfg.name,
cfg.get_tgt_attr())
if not os.path.isdir(tgt_root): continue
arch_md5 = sys_utils.md5_file(arch_cfg)
rtl_path = (os.path.join(rtl_root, 'common'),
os.path.join(rtl_root,
'memory'), os.path.join(rtl_root,
'top'), tgt_root)
t_wd = get_target_out_dir(cfg.get_tgt_sig(), arch_md5, run_root)
lib_path = os.path.join(t_wd, 'hw-libs')
solver_rtl_gen.generate_rtl_package(
cfg,
lib_path,
rtl_path=rtl_path,
tb_path=(os.path.join(rtl_root, 'testbench'), ),
def_path=(os.path.join(rtl_root, 'define'), ),
target=target,
tb_module='simd_top_testbench',
lib='work')
sim_wd = os.path.join(lib_path, '%s_wd' % flow)
# Check if it is necessary to compile the simulation libraries
check_and_compile_solver_rtl(lib_path,
sim_wd,
flow,
sim_cc,
stdout=stdout,
stderr=stderr)
def run_solver_bin_ar(bin_ar, arch_config, rtl_root, run_root, sim_out=None,
target='generic', flow='vsim', stdout=None, stderr=None):
global VERBOSE
if not os.access(arch_config, os.R_OK):
raise RuntimeError('Invalid architecture config "%s"'%arch_config)
arch_md5 = sys_utils.md5_file(arch_config)
cfg = read_arch_config(arch_config)
tgt_sig = cfg.get_tgt_sig()
sim_cc, sim_exe = sim_utils.get_rtl_tools(flow)
sys_utils.mkdir_p(os.path.abspath(run_root))
t_wd = get_target_out_dir(cfg.get_tgt_sig(), arch_md5, run_root)
lib_path = os.path.join(t_wd, 'hw-libs')
# If RTL folder does not exist, generate it from config file
if not os.path.isdir(lib_path):
tgt_rtl_root = os.path.join(rtl_root,'core',cfg.name,cfg.get_tgt_attr())
rtl_path = (os.path.join(rtl_root, 'common'),
os.path.join(rtl_root, 'memory'),
os.path.join(rtl_root, 'top'), tgt_rtl_root)
solver_rtl_gen.generate_rtl_package(
cfg, lib_path, rtl_path=rtl_path,
tb_path = (os.path.join(rtl_root, 'testbench'),),
def_path = (os.path.join(rtl_root, 'define'),),
target=target, tb_module='simd_top_testbench', lib='work')
sim_wd = os.path.join(lib_path, '%s_wd'%flow)
# Check if it is necessary to compile the simulation libraries
check_and_compile_solver_rtl(lib_path, sim_wd, flow, sim_cc,
stdout=stdout, stderr=stderr)
# Setup application files
clean_solver_rtl_simulation(sim_wd)
app_name = sys_utils.get_path_basename(bin_ar)
setup_solver_mem_files(bin_ar, sim_wd)
# Run the actual simulation
run_solver_rtl_simulation(sim_exe, sim_wd, flow, lib_path, cfg,
stdout=stdout, stderr=stderr, gui=False)
if not sim_out: sim_out = os.path.join(t_wd, 'sim-out', app_name)
move_dump_files(sim_wd, sim_out)
cfg = read_arch_config(args[0])
tgt_attr = '%db-%dstage'%(cfg.cp.datapath['data_width'],
cfg.cp.datapath['pipe_stage'])
if cfg.cp.datapath['explicit_bypass']: tgt_attr += '-bypass'
tgt_rtl_root = os.path.join(opts.solver_rtl_root,'core',cfg.name,tgt_attr)
if not opts.gen_dir:
opts.gen_dir = os.path.join(
os.path.abspath(CWD), 'RTL-%s-%s'%(cfg.name, tgt_attr))
rtl_path = [os.path.join(opts.solver_rtl_root, 'common'),
os.path.join(opts.solver_rtl_root, 'memory'),
os.path.join(opts.solver_rtl_root, 'top'), tgt_rtl_root]
solver_rtl_gen.VERBOSE = VERBOSE
if opts.xil_pcore:
solver_rtl_gen.generate_xil_pcore(
cfg, out_dir=opts.gen_dir, rtl_path=rtl_path, target=opts.target,
def_path=(os.path.join(opts.solver_rtl_root, 'define'),),
sys_path=os.path.join(opts.solver_rtl_root, 'system'))
shutil.copy2(args[0], os.path.join(opts.gen_dir, 'arch.json'))
else:
solver_rtl_gen.generate_rtl_package(
cfg, opts.gen_dir, rtl_path=rtl_path,
tb_path = (os.path.join(opts.solver_rtl_root, 'testbench'),),
def_path = (os.path.join(opts.solver_rtl_root, 'define'),),
target=opts.target, tb_module='simd_top_testbench', lib='work',
asic_lib_cfg=opts.synth_lib)
shutil.copy2(args[0], os.path.join(opts.gen_dir, 'arch.json'))
opts.gen_dir = os.path.join(os.path.abspath(CWD),
'RTL-%s-%s' % (cfg.name, tgt_attr))
rtl_path = [
os.path.join(opts.solver_rtl_root, 'common'),
os.path.join(opts.solver_rtl_root, 'memory'),
os.path.join(opts.solver_rtl_root, 'top'), tgt_rtl_root
]
solver_rtl_gen.VERBOSE = VERBOSE
if opts.xil_pcore:
solver_rtl_gen.generate_xil_pcore(
cfg,
out_dir=opts.gen_dir,
rtl_path=rtl_path,
target=opts.target,
def_path=(os.path.join(opts.solver_rtl_root, 'define'), ),
sys_path=os.path.join(opts.solver_rtl_root, 'system'))
shutil.copy2(args[0], os.path.join(opts.gen_dir, 'arch.json'))
else:
solver_rtl_gen.generate_rtl_package(
cfg,
opts.gen_dir,
rtl_path=rtl_path,
tb_path=(os.path.join(opts.solver_rtl_root, 'testbench'), ),
def_path=(os.path.join(opts.solver_rtl_root, 'define'), ),
target=opts.target,
tb_module='simd_top_testbench',
lib='work',
asic_lib_cfg=opts.synth_lib)
shutil.copy2(args[0], os.path.join(opts.gen_dir, 'arch.json'))
