# Activate command : cs ras cas we : L L H H
sd_intf.cs.next,sd_intf.ras.next,sd_intf.cas.next,sd_intf.we.next = 0,0,1,1
sd_intf.cke.next = 1
yield delay(10)
sd_intf.addr.next = 2
sd_intf.we.next = 1
yield delay(5)
dqDriver.next = 123
yield delay(10)
sd_intf.we.next = 0
dqDriver.next = None
yield delay(20)
sd_intf.addr.next = 1
yield delay(20)
sd_intf.addr.next = 2
yield delay(20)
sd_intf.addr.next = 3
clk = Signal(bool(0))
# module instances
clkDriver_inst = clkDrive(clk)
sdram_intf = sd_intf(clk)
sdram_inst = sdram(sdram_intf)
writeData_inst = writeData(sdram_intf)
activateTest_inst = activateTest(sdram_intf)
sim = Simulation(clkDriver_inst, sdram_inst, activateTest_inst)
sim.run(100)
yield delay(10000)
yield sd_intf.loadMode(clk)
yield sd_intf.nop(clk)
yield sd_intf.activate(clk, 17)
yield sd_intf.nop(clk)
yield delay(10000)
yield sd_intf.write(clk, driver, 20, 31)
#yield delay(5)
yield sd_intf.nop(clk)
yield delay(100)
yield sd_intf.read(clk, 20)
#yield delay(10)
yield sd_intf.nop(clk)
yield delay(4)
print "sd_intf dq = ", sd_intf.dq.val, " @ ", now()
return test
clk = Signal(bool(0))
clkDriver_Inst = clkDriver(clk)
sd_intf_Inst = sd_intf()
sdram_Inst = sdram(clk, sd_intf_Inst)
test_readWrite_Inst = test_readWrite(clk, sd_intf_Inst)
sim = Simulation(clkDriver_Inst, sdram_Inst, test_readWrite_Inst)
sim.run(25000)
yield sd_intf.nop(clk)
yield delay(10000)
yield sd_intf.loadMode(clk)
yield sd_intf.nop(clk)
yield sd_intf.activate(clk,17)
yield sd_intf.nop(clk)
yield delay(10000)
yield sd_intf.write(clk,driver,20,31)
#yield delay(5)
yield sd_intf.nop(clk)
yield delay(100)
yield sd_intf.read(clk,20)
#yield delay(10)
yield sd_intf.nop(clk)
yield delay(4)
print "sd_intf dq = ",sd_intf.dq.val," @ ",now()
return test
clk = Signal(bool(0))
clkDriver_Inst = clkDriver(clk)
sd_intf_Inst = sd_intf()
sdram_Inst = sdram(clk,sd_intf_Inst)
test_readWrite_Inst = test_readWrite(clk,sd_intf_Inst)
sim = Simulation(clkDriver_Inst,sdram_Inst,test_readWrite_Inst)
sim.run(25000)