def runtest():
latch = PulseLatch('latch',
t_data_2_clr=5.0,
t_clr_2_data=5.0,
t_out_delay=2.)
din = Signal('d_in')
clr = Signal('clr')
latch.connect('input', din)
latch.connect('clr', clr)
din.trace()
clr.trace()
latch.output.trace()
SEQ.addall([
setsig(5.0, din, 77),
setsig(20.0, clr, '!'),
setsig(40.0, din, 35),
])
latchview = PulseLatchView(latch,
input_xy=(0, 10),
output_xy=(0, 2),
value_text_kwargs={'fontsize': 60})
scene = [latchview]
ax = viz(
scene,
until_seqtime=350.0,
# speedup_factor=10.0,
speedup_factor=5.0,
frame_interval_secs=0.05,
pause_in_gaps=True)
# skip_gaps = True)
# pause_every_step=True)
print('\n\nRETURN TO EXIT...>')
six.moves.input()
from sim.bbc.controller import BbcController
from sim.signal import Signal
from sim.sequencer import DEFAULT_SEQUENCER as SEQ
from sim.tests import setsig
cycle = BbcController()
print(cycle)
sig_start = Signal('start')
sig_start.trace()
cycle.connect('start', sig_start)
cycle.current_phase.trace()
# cycle.trace('_do_phase')
for phase_name, _ in cycle.phase_names_and_default_durations:
getattr(cycle, phase_name).trace()
SEQ.add(setsig(0.0, sig_start, '!'))
SEQ.run(100.0)
SEQ.clear() # Clear out unfinished business, so other tests can run!
counter.connect('clear', clr)
din.trace()
clr.trace()
counter.output.trace()
counter.x_carry_out.trace()
# for bit_counter in counter._bit_counters:
# bit_counter.output.trace()
# bit_counter.x_carry_out.trace()
#
# for carry_gate in counter._carry_gates:
# carry_gate.output.trace()
SEQ.addall([
setsig(100.0, din, 1),
setsig(120.0, din, 1),
setsig(140.0, din, 1),
setsig(160.0, din, 1),
])
COUNTER_CARRYOUTS_COUNT = 0
def carry_out_callback(time, signal):
global COUNTER_CARRYOUTS_COUNT
COUNTER_CARRYOUTS_COUNT += 1
counter.x_carry_out.add_connection(carry_out_callback)
from sim.tests import okeq, okin, setsig, fails
latch = PulseLatch('latch', t_data_2_clr=2.0, t_clr_2_data=2.0, t_out_delay=5.)
din = Signal('d_in')
clr = Signal('clr')
latch.connect('input', din)
latch.connect('clr', clr)
din.trace()
clr.trace()
latch.output.trace()
print('\ncheck set, clr, set')
SEQ.addall([
setsig(100.0, din, 77),
setsig(200.0, clr, '!'),
setsig(250.0, din, 35),
])
SEQ.run(10)
okeq(latch.output.state, 0)
SEQ.run(100.1)
okeq(latch.output.state, SIG_UNDEF)
SEQ.run(105.1)
okeq(latch.output.state, 77)
SEQ.run(200.1)
okeq(latch.output.state, SIG_UNDEF)
SEQ.run(204.9)
okeq(latch.output.state, SIG_UNDEF)
SEQ.run(205.1)
okeq(latch.output.state, 0)
d_a0 = sig_bitslice(sig_a, 0)
d_a2 = sig_bitslice(sig_a, 2, name='a2_x')
d_a12 = sig_bitslice(sig_a, 1, nbits=2)
okeq(d_a0.name, 'a:0')
okeq(d_a2.name, 'a2_x')
okeq(d_a12.name, 'a:1..2')
a0 = d_a0.output
a2 = d_a2.output
a12 = d_a12.output
okeq(a0.name, 'a:0.output')
okeq(a2.name, 'a2_x.output')
okeq(a12.name, 'a:1..2.output')
print('\ncheck bit slices')
SEQ.addall([
setsig(100.0, sig_a, 0b0101),
setsig(200.0, sig_a, SIG_UNDEF),
setsig(300.0, sig_a, 0b0010),
])
SEQ.run(10.)
okeq(a0.state, 0)
okeq(a2.state, 0)
okeq(a12.state, 0)
SEQ.run(100.)
okeq(a0.state, 1)
okeq(a2.state, 1)
okeq(a12.state, 0b10)
SEQ.run(200.)
okeq(a0.state, SIG_UNDEF)
aclr = Signal('!a_aclr')
ram.connect('d_in', d_in)
ram.connect('addr', addr)
ram.connect('x_read', ard)
ram.connect('x_aclr', aclr)
addr.trace()
d_in.trace()
ard.trace()
aclr.trace()
ram.out.trace()
print('\ncheck set, clr')
SEQ.addall([
setsig(100.0, addr, 3),
setsig(110.0, ard, '!'),
setsig(112.0, aclr, '!'),
])
SEQ.run()
okeq(ram.out.state, 0)
print('\ncheck read, write')
SEQ.addall([
setsig(100.0, addr, 2),
setsig(110.0, ard, '!'),
setsig(120.0, d_in, 213),
setsig(122.0, aclr, '!'),
])
SEQ.run()
okeq(ram.out.state, 0)
clr.trace()
counter.output.trace()
counter.x_carry_out.trace()
COUNTER_CARRYOUTS_COUNT = 0
def carry_out_callback(time, signal):
global COUNTER_CARRYOUTS_COUNT
COUNTER_CARRYOUTS_COUNT += 1
counter.x_carry_out.add_connection(carry_out_callback)
SEQ.addall([
setsig(100.0, din, 1),
setsig(110.0, din, 1),
setsig(120.0, din, 1),
setsig(150.0, clr, 1),
setsig(160.0, clr, 0),
setsig(180.0, clr, 1),
setsig(181.0, ore, 1),
setsig(190.0, clr, 0),
setsig(200.0, din, 1),
setsig(210.0, din, 1),
setsig(220.0, din, 1),
setsig(223.0, clr, 0),
])
okeq(counter.output.state, 0)
okeq(COUNTER_CARRYOUTS_COUNT, 0)
addr = Signal('addr')
aen = Signal('!a_ena')
aclr = Signal('!a_dis')
read = Signal('!read')
rom.connect('addr', addr)
rom.connect('x_asel', aen)
rom.connect('x_aclr', aclr)
rom.connect('x_read', read)
addr.trace()
aen.trace()
aclr.trace()
read.trace()
rom.out.trace()
print('\ncheck set, clr, set')
SEQ.addall([
setsig(100.0, addr, 3),
setsig(110.0, aen, '!'),
setsig(115.0, read, '!'),
setsig(120.0, aclr, '!'),
setsig(200.0, addr, 1),
setsig(210.0, aen, '!'),
setsig(215.0, read, '!'),
setsig(220.0, aclr, '!'),
])
SEQ.run(150.)
okeq(rom.out.state, 42)
SEQ.run()
okeq(rom.out.state, 4)