def test_on_falling_edge(self):
"Tests on_falling_edge method"
pc4e = Bus(32)
regwre = Bus(1)
memwre = Bus(1)
regsrce = Bus(1)
wd3se = Bus(1)
rd2e = Bus(32)
fe = Bus(32)
ra3e = Bus(4)
clk = Bus(1)
pc4m = Bus(32)
regwrm = Bus(1)
memwrm = Bus(1)
regsrcm = Bus(1)
wd3sm = Bus(1)
fm = Bus(32)
rd2m = Bus(32)
ra3m = Bus(4)
exmem = Exmem(pc4e, regwre, memwre, regsrce, wd3se, rd2e, fe, ra3e,
clk, pc4m, regwrm, memwrm, regsrcm, wd3sm, fm, rd2m,
ra3m, Latch_Type.FALLING_EDGE)
memwre.write(1)
self.assertNotEqual(memwre.read(), memwrm.read())
exmem.on_falling_edge()
self.assertEqual(memwre.read(), memwrm.read())
def test_run(self):
"Prove that PC is routed from external signal to read"
clk = Bus(1, 0)
rst = Bus(1, 0)
wa = Bus(4, 0)
wd = Bus(32, 10)
ra0 = Bus(4, 0)
ra1 = Bus(4, 0)
ra2 = Bus(4, 0)
rd0 = Bus(32)
rd1 = Bus(32)
rd2 = Bus(32)
en = Bus(1, 0)
pc = Bus(32, 0)
reg = RegisterFile(clk, rst, en, wd, ra0, ra1, ra2, wa, rd0, rd1, rd2,
pc)
# set buses
pc.write(255)
ra0.write(15)
ra1.write(15)
ra2.write(1)
#run and validate
reg.run()
self.assertEqual(rd0.read(), 255)
self.assertEqual(rd1.read(), 255)
self.assertNotEqual(rd2.read(), 255)
def test_run(self):
"Prove correct combinational output given signals"
c0 = Constant(8, 150)
c1 = Constant(8, 5)
c2 = Constant(8, 255)
s = Bus(2, 0)
y = Bus(8, 1)
m = Mux(8, [c0, c1, c2], s, y)
m.run()
self.assertTrue(y.read() == c0.read())
s.write(1)
m.run()
self.assertTrue(y.read() == c1.read())
s.write(2)
m.run()
self.assertTrue(y.read() == c2.read())
s.write(3)
m.run()
self.assertTrue(y.read() == 0)
s.write(0)
m = Mux(8, [c0, c1, c2], s)
m.run()
def test_run(self):
"""
tests the enxtender's run function
"""
imm = Bus(24)
imm32 = Bus(32)
exts = Bus(2)
# initialize extender
e = Extender(imm, exts, imm32)
# initialize input with value 5096
imm.write(0b000000000001001111101000)
# test case 4
exts.write(0)
e.run()
self.assertEqual(imm32.read(), 0xA0000003)
# test case 5
exts.write(1)
e.run()
self.assertEqual(imm32.read(), 0b001111101000)
# test case 6
exts.write(2)
e.run()
self.assertEqual(imm32.read(), 0b100111110100000)
# test case 7
imm.write(0b100000000001001111101000)
e.run()
self.assertEqual(imm32.read(), 0b11111110000000000100111110100000)
def test_run(self):
"Tests the run method"
pc4e = Bus(32)
regwre = Bus(1)
memwre = Bus(1)
regsrce = Bus(1)
wd3se = Bus(1)
rd2e = Bus(32)
fe = Bus(32)
ra3e = Bus(4)
clk = Bus(1)
pc4m = Bus(32)
regwrm = Bus(1)
memwrm = Bus(1)
regsrcm = Bus(1)
wd3sm = Bus(1)
fm = Bus(32)
rd2m = Bus(32)
ra3m = Bus(4)
exmem = Exmem(pc4e, regwre, memwre, regsrce, wd3se, rd2e, fe, ra3e,
clk, pc4m, regwrm, memwrm, regsrcm, wd3sm, fm, rd2m,
ra3m)
rd2e.write(0xE24AA020)
ra3e.write(4)
exmem.run()
self.assertNotEqual(rd2e.read(), rd2m.read())
self.assertNotEqual(ra3e.read(), ra3m.read())
clk.write(1)
exmem.run()
self.assertEqual(rd2e.read(), rd2m.read())
self.assertEqual(ra3e.read(), ra3m.read())
def test_on_rising_edge(self):
"Tests the on_rising_edge method"
pc4m = Bus(32)
regwrm = Bus(1)
regsrcm = Bus(1)
wd3sm = Bus(1)
fm = Bus(32)
rdm = Bus(32)
ra3m = Bus(4)
clk = Bus(1)
pc4w = Bus(32)
regwrw = Bus(1)
regsrcw = Bus(1)
wd3sw = Bus(1)
fw = Bus(32)
rdw = Bus(32)
ra3w = Bus(4)
memwb = Memwb(pc4m, regwrm, regsrcm, wd3sm, fm, rdm, ra3m, clk, pc4w,
regwrw, regsrcw, wd3sw, fw, rdw, ra3w)
regsrcm.write(1)
wd3sm.write(1)
self.assertNotEqual(regsrcm.read(), regsrcw.read())
self.assertNotEqual(wd3sm.read(), wd3sw.read())
memwb.on_rising_edge()
self.assertEqual(regsrcm.read(), regsrcw.read())
self.assertEqual(wd3sm.read(), wd3sw.read())
def test_modify(self):
"Verifies internal hook modify function"
clk = Bus(1, 0)
rst = Bus(1, 0)
d_bus = Bus(8, 0)
q_bus = Bus(8, 0)
reg = Register(8, clk, rst, d_bus, q_bus, 1)
tm = None
rm = reg.modify(tm)
self.assertTrue('error' in rm)
tm = {}
rm = reg.modify(tm)
self.assertTrue('error' in rm)
tm = {'state': '0'}
rm = reg.modify(tm)
self.assertTrue('error' in rm)
tm = {'state': -1}
rm = reg.modify(tm)
self.assertTrue('error' in rm)
tm = {'state': 256}
rm = reg.modify(tm)
self.assertTrue('error' in rm)
tm = {'state': 128}
rm = reg.modify(tm)
self.assertTrue('success' in rm and rm['success'])
reg.run()
self.assertTrue(q_bus.read() == 128)
def test_run(self):
"Prove correct combinational output given signals"
cin = Constant(1, 1)
c1 = Constant(8, 1)
c2 = Constant(8, 254)
y0 = Bus(8)
cout = Bus(1)
a = Adder(8, c1, c2, y0, cin, cout)
a.run()
self.assertTrue(y0.read() == 0)
self.assertTrue(cout.read() == 1)
a.run(50)
self.assertTrue(y0.read() == 0)
self.assertTrue(cout.read() == 1)
def test_run(self):
"""
tests the memory's run function
"""
ad = Bus(32, 0)
rst = Bus(1, 0)
rd = Bus(32, 0)
mem = ProgramMemory(ad, rst, rd, default_size=32)
# "flash" data to program memory
data = []
for i in range(0, 32):
data.append(i + 1)
msg = mem.modify({'start': 0, 'data': data})
# read from memory validating "programming"
for i in range(0, 8):
ad.write(i * 4)
mem.run()
word = 0
for j in range(0, 4):
word |= data[i * 4 + j] << (32 - ((j + 1) * 8))
self.assertEqual(rd.read(), word)
# test clear message proving empty
mem.clear()
msg = mem.inspect()
self.assertEqual(len(msg['state'].keys()), 0)
def test_run(self):
"Prove correct combinational output given signals"
c0 = Constant(16, 0xAAAA)
b0 = Bus(4)
b1 = Bus(8)
b2 = Bus(2)
b3 = Bus(2)
b4 = Bus(1)
bs = BusSubset(c0, [b0, b1, b2, b3, b4], [(0, 4), (4, 12), (12, 14),
(14, 16), (3, 4)])
bs.run()
self.assertTrue(b0.read() == 0x0A)
self.assertTrue(b1.read() == 0xAA)
self.assertTrue(b2.read() == 0x02)
self.assertTrue(b3.read() == 0x02)
self.assertTrue(b4.read() == 1)
def test_on_rising_edge(self):
"Tests on_rising_edge method"
pc4f = Bus(32)
pc8f = Bus(32)
instrf = Bus(32)
stall = Bus(1)
flush = Bus(1)
clk = Bus(1)
pc4d = Bus(32)
pc8d = Bus(32)
instrd = Bus(32)
ifid = Ifid(pc4f, pc8f, instrf, stall, flush, clk, pc8d, pc8d, instrd)
instrf.write(0xE3A0800A) # mov r8, #10
self.assertNotEqual(instrf.read(), instrd.read())
ifid.on_rising_edge()
self.assertEqual(instrf.read(), instrd.read())
def test_run(self):
"""
tests the memory's run function
"""
ad = Bus(32, 0)
wd = Bus(32, 0)
we = Bus(1, 0)
rst = Bus(1, 0)
clk = Bus(1, 0)
rd = Bus(32, 0)
mem = DataMemory(ad, wd, we, rst, clk, rd, default_size=16, default_value=0x81)
# write to memory cells
we.write(1)
for i in range(0, 4):
ad.write(4 * i)
wd.write(i * 25)
clk.write(0)
mem.run()
clk.write(1)
mem.run()
clk.write(0)
mem.run()
# insect memory contents
msg = mem.inspect()
self.assertTrue(len(msg['state'].keys()) == 16)
# read from memory cells
we.write(0)
for i in range(0, 4):
ad.write(4 * i)
mem.run()
self.assertEqual(rd.read(), i * 25)
# check reset behavior
rst.write(1)
mem.run()
rst.write(0)
for i in range(0, 4):
ad.write(4 * i)
mem.run()
self.assertEqual(rd.read(), 0x81818181)
def test_on_falling_edge(self):
"Tests on_falling edge method"
pc4d = Bus(32)
regwrd = Bus(1)
alusrcbd = Bus(1)
alusd = Bus(4)
aluflagwrd = Bus(1)
memwrd = Bus(1)
regsrcd = Bus(1)
wd3sd = Bus(1)
rd1d = Bus(32)
rd2d = Bus(32)
imm32d = Bus(32)
ra1d = Bus(4)
ra2d = Bus(4)
ra3d = Bus(4)
flush = Bus(1)
clk = Bus(1)
pc4e = Bus(32)
regwre = Bus(1)
alusrcbe = Bus(1)
aluse = Bus(4)
aluflagwre = Bus(1)
memwre = Bus(1)
regsrce = Bus(1)
wd3se = Bus(1)
rd1e = Bus(32)
rd2e = Bus(32)
imm32e = Bus(32)
ra1e = Bus(4)
ra2e = Bus(4)
ra3e = Bus(4)
idex = Idex(pc4d, regwrd, alusrcbd, alusd, aluflagwrd, memwrd, regsrcd,
wd3sd, rd1d, rd2d, imm32d, ra1d, ra2d, ra3d, flush, clk,
pc4e, regwre, alusrcbe, aluse, aluflagwre, memwre, regsrce,
wd3se, rd1e, rd2e, imm32e, ra1e, ra2e, ra3e,
edge_type=Latch_Type.FALLING_EDGE)
pc4d.write(48)
self.assertNotEqual(pc4d.read(), pc4e.read())
idex.on_falling_edge()
self.assertEqual(pc4d.read(), pc4e.read())
def test_run(self):
"Prove correct combinational output given signals"
c1 = Constant(1, 1)
c2 = Constant(2, 0)
c3 = Constant(3, 7)
b = Bus(6)
bj = BusJoin([c1, c2, c3], b)
bj.run()
self.assertTrue(b.read() == 0x39)
def test_reset(self):
"Verifies reset behavior of component"
clk = Bus(1, 0)
rst = Bus(1, 0)
d_bus = Bus(8, 10)
q_bus = Bus(8, 0)
reg = Register(8, clk, rst, d_bus, q_bus, 0, Latch_Type.RISING_EDGE,
Logic_States.ACTIVE_HIGH)
clk.write(0)
reg.run()
self.assertTrue(q_bus.read() == 0)
clk.write(1)
reg.run()
self.assertTrue(q_bus.read() == 10)
reg.on_reset()
reg.run()
self.assertTrue(q_bus.read() == 0)
def test_on_falling_edge(self):
"Tests on_falling_edge method"
pc4f = Bus(32)
pc8f = Bus(32)
instrf = Bus(32)
stall = Bus(1)
flush = Bus(1)
clk = Bus(1)
pc4d = Bus(32)
pc8d = Bus(32)
instrd = Bus(32)
ifid = Ifid(pc4f, pc8f, instrf, stall, flush, clk, pc4d, pc8d, instrd,
0, Latch_Type.FALLING_EDGE, Logic_States.ACTIVE_LOW, None,
Logic_States.ACTIVE_HIGH)
instrf.write(0xE3A0800A) # mov r8, #10
flush.write(1)
self.assertNotEqual(instrf.read(), instrd.read())
ifid.on_falling_edge()
self.assertEqual(instrf.read(), instrd.read())
def test_run(self):
"Verifies correct time based simulation"
clk = Bus(1, 0)
rst = Bus(1, 0)
wa = Bus(4, 0)
wd = Bus(8, 10)
ra0 = Bus(4, 0)
ra1 = Bus(4, 0)
rd0 = Bus(8)
rd1 = Bus(8)
en = Bus(1, 0)
rgf = RegisterFile(16, 8, clk, rst, wa, wd, [ra0, ra1], [rd0, rd1], en)
# write to each register
en.write(1)
for i in range(16):
wa.write(i)
wd.write(i + 1)
clk.write(0)
rgf.run()
clk.write(1)
rgf.run()
clk.write(0)
rgf.run()
# read from each register seperate
for i in range(8):
ra0.write(i)
ra1.write(i + 8)
rgf.run()
self.assertTrue(rd0.read() == i + 1)
self.assertTrue(rd1.read() == i + 9)
# read same location to verify data
for i in range(16):
ra0.write(i)
ra1.write(i)
rgf.run()
self.assertTrue(rd0.read() == rd1.read())
def test_rising_edge(self):
"Verifies rising edge capture behavior"
clk = Bus(1, 0)
rst = Bus(1, 0)
d_bus = Bus(8, 10)
q_bus = Bus(8, 0)
reg = Register(8, clk, rst, d_bus, q_bus, 0, Latch_Type.RISING_EDGE,
Logic_States.ACTIVE_HIGH)
reg.run()
self.assertTrue(q_bus.read() == 0)
d_bus.write(15)
reg.on_rising_edge()
reg.run()
self.assertTrue(q_bus.read() == 15)
d_bus.write(25)
reg.on_falling_edge()
reg.run()
self.assertTrue(q_bus.read() == 15)
def test_run(self):
"Test run method"
pc4f = Bus(32)
pc8f = Bus(32)
instrf = Bus(32)
stall = Bus(1)
flush = Bus(1)
clk = Bus(1)
pc4d = Bus(32)
pc8d = Bus(32)
instrd = Bus(32)
ifid = Ifid(pc4f, pc8f, instrf, stall, flush, clk, pc4d, pc8d, instrd)
instrf.write(0xE24AA020) # sub r10, r10, #32
ifid.run()
self.assertNotEqual(instrf.read(), instrd.read())
clk.write(1)
ifid.run()
self.assertEqual(instrf.read(), instrd.read())
clk.write(0)
ifid.run()
clk.write(1)
flush.write(1)
ifid.run()
self.assertNotEqual(instrf.read(), instrd.read())
def test_out_of_bounds(self):
"Test for valid control signal that extends past defined"
c0 = Constant(8, 150)
c1 = Constant(8, 5)
c2 = Constant(8, 255)
s = Bus(2, 0)
y = Bus(8, 1)
m = Mux(8, [c0, c1, c2], s, y)
s.write(3)
m.run()
self.assertTrue(y.read() == 0) # prove valid overflow
def test_run(self):
"Verifies correct time based simulation"
clk = Bus(1, 0)
rst = Bus(1, 0)
d_bus = Bus(8, 10)
q_bus = Bus(8, 0)
en = Bus(1, 0)
reg = Register(8, clk, rst, d_bus, q_bus, 0, Latch_Type.RISING_EDGE,
Logic_States.ACTIVE_HIGH, en, Logic_States.ACTIVE_HIGH)
en.write(0)
clk.write(0)
reg.run()
self.assertTrue(q_bus.read() == 0)
en.write(1)
clk.write(0)
reg.run()
self.assertTrue(q_bus.read() == 0)
en.write(0)
clk.write(1)
reg.run()
self.assertTrue(q_bus.read() == 0)
en.write(1)
clk.write(1)
reg.run()
self.assertTrue(q_bus.read() == 0)
clk.write(0)
reg.run()
self.assertTrue(q_bus.read() == 0)
clk.write(1)
reg.run()
self.assertTrue(q_bus.read() == 10)
d_bus.write(15)
clk.write(0)
reg.run()
self.assertTrue(q_bus.read() == 10)
rst.write(1)
clk.write(1)
reg.run()
self.assertTrue(q_bus.read() == 0)
def test_constructor(self):
"Constructor with valid and invalid configuration"
with self.assertRaises(TypeError):
b = Bus('0')
with self.assertRaises(TypeError):
b = Bus(0)
with self.assertRaises(TypeError):
b = Bus(1, -1)
with self.assertRaises(TypeError):
b = Bus(1, 2)
with self.assertRaises(TypeError):
b = Bus(1, '0')
b = Bus(8, 255)
self.assertTrue(b.read() == 255)
self.assertTrue(b.size() == 8)
def test_run(self):
"Tests the run method"
ra1e = Bus(4)
ra2e = Bus(4)
ra3e = Bus(4)
ra3m = Bus(4)
ra3w = Bus(4)
regwrm = Bus(1)
regwrw = Bus(1)
regsrcm = Bus(1)
regsrcw = Bus(1)
memwrm = Bus(1)
pcsrcd = Bus(2)
fwda = Bus(3)
fwdb = Bus(3)
fwds = Bus(1)
stallf = Bus(1)
flushf = Bus(1)
flushd = Bus(1)
hazard_controller = HazardController(ra1e, ra2e, ra3e, ra3m, ra3w,
regwrm, regwrw, regsrcm, regsrcw,
memwrm, pcsrcd, fwda, fwdb, fwds,
stallf, flushf, flushd)
# fwda output expected to be 3
ra1e.write(4)
ra3w.write(4)
regsrcw.write(1)
# fwdb output expected to be 0
# fwds output expected to be 1
ra3m.write(4)
memwrm.write(1)
# stallf output expected to be 1
pcsrcd.write(2)
# flushf output expected to be 0
# flushd output expected to be 0
hazard_controller.run()
self.assertEqual(fwda.read(), 3)
self.assertEqual(fwdb.read(), 0)
self.assertEqual(fwds.read(), 1)
self.assertEqual(stallf.read(), 1)
self.assertEqual(flushf.read(), 0)
self.assertEqual(flushd.read(), 0)
def test_run(self):
"""
Test combinational run behavior
"""
x = Bus(32)
s = Bus(2)
y = Bus(32)
mrse = MemoryReadSignExtender(x, s, y)
# disabled extend (pass through)
x.write(0xFF)
s.write(0)
mrse.run()
self.assertEqual(y.read(), 0xFF)
# disabled extend (pass through)
x.write(0xF2C8FF)
s.write(2)
mrse.run()
self.assertEqual(y.read(), 0xF2C8FF)
# enable extend byte
x.write(0x2CAE)
s.write(1)
mrse.run()
self.assertEqual(y.read(), 0xFFFFFFAE)
x.write(0x2C5E)
s.write(1)
mrse.run()
self.assertEqual(y.read(), 0x5E)
#enable extend half-word
x.write(0x34ACAE)
s.write(3)
mrse.run()
self.assertEqual(y.read(), 0xFFFFACAE)
x.write(0xF2C5E)
s.write(3)
mrse.run()
self.assertEqual(y.read(), 0x2C5E)
def test_run(self):
"Tests the pipeline processors run method"
cond = Bus(4)
op = Bus(2)
funct = Bus(6)
rd = Bus(4)
bit4 = Bus(1)
c = Bus(1)
v = Bus(1)
n = Bus(1)
z = Bus(1)
stalld = Bus(1)
pcsrcd = Bus(2)
pcwrd = Bus(1)
regsad = Bus(1)
regdstd = Bus(2)
regwrsd = Bus(2)
regwrd = Bus(1)
extsd = Bus(2)
alusrcbd = Bus(1)
alusd = Bus(4)
aluflagwrd = Bus(1)
memwrd = Bus(1)
regsrcd = Bus(1)
wd3sd = Bus(1)
# initialize single cycle controller
pp = ControllerPipeline(cond, op, funct, rd, bit4, c, v, n, z, stalld,
pcsrcd, pcwrd, regsad, regdstd, regwrsd,
regwrd, extsd, alusrcbd, alusd, aluflagwrd,
memwrd, regsrcd, wd3sd)
# pcsrcd tests
# test case 4 - occurs for banch instructions where condition is met
op.write(2)
cond.write(1)
pp.run()
self.assertEqual(pcsrcd.read(), 0)
# test case 5 - occurs when a data processing instruction modifies pc
op.write(0)
rd.write(15)
pp.run()
self.assertEqual(pcsrcd.read(), 2)
# test case 6 - for pc+4
op.write(1)
pp.run()
self.assertEqual(pcsrcd.read(), 1)
# pcwrd
# test case 7 - always write
self.assertEqual(pcwrd.read(), 1)
# regsad
# test case 8 - used to select Rn register (mul instruction)
op.write(0)
bit4.write(1)
funct.write(1)
pp.run()
self.assertEqual(regsad.read(), 0)
# test case 9 - used to select Rn register (data processing instuction)
op.write(1)
pp.run()
self.assertEqual(regsad.read(), 1)
# regdstd
# test case 10 - used to select Rd register (str instruction)
op.write(1)
funct.write(24)
pp.run()
self.assertEqual(regdstd.read(), 2)
# test case 11 - used to select Rm register (data processing instruction)
op.write(0)
bit4.write(1)
funct.write(0)
pp.run()
self.assertEqual(regdstd.read(), 0)
# test case 12 - used to select Rm register (mul instruction)
op.write(2)
pp.run()
self.assertEqual(regdstd.read(), 1)
# regwrsd
# test cast 13 - used to select lr instruction (bl instruction)
op.write(2)
funct.write(16)
pp.run()
self.assertEqual(regwrsd.read(), 2)
# test case 14 - used to select Rd register (data processing instruction)
op.write(0)
bit4.write(1)
funct.write(0)
pp.run()
self.assertEqual(regwrsd.read(), 0)
# test case 15 - used to selcet Rd resister (mul instruction)
op.write(1)
pp.run()
self.assertEqual(regwrsd.read(), 1)
# regwrd
# test case 16 - occurs when an instruction writes back to the regfile
op.write(0)
funct.write(53)
pp.run()
self.assertEqual(regwrd.read(), 0)
# test case 17 - occurs when an instruction writes back to the regfile
op.write(1)
funct.write(24)
pp.run()
self.assertEqual(regwrd.read(), 0)
# test case 18 - occurs when an instruction writes back to the regfile
op.write(2)
funct.write(0b101100)
pp.run()
self.assertEqual(regwrd.read(), 0)
# test case 19 - occurs when an instruction writes back to the regfile
funct.write(0b010000)
pp.run()
self.assertEqual(regwrd.read(), 1)
# extsd
# test case 20 - used for branch instruction
op.write(2)
pp.run()
self.assertEqual(extsd.read(), 2)
# test case 21 - used for 12-bit immediate (ldr and str instructions)
op.write(1)
funct.write(25)
pp.run()
self.assertEqual(extsd.read(), 1)
# test case 22 - used for 8-bit immediate (data processing immediate)
op.write(0)
pp.run()
self.assertEqual(extsd.read(), 0)
# alusrcbd
# test case 23 - occurs when source b requires the output to the rd2 register
# (data processing instruction)
op.write(0)
funct.write(28)
pp.run()
self.assertEqual(alusrcbd.read(), 1)
# test case 24 - occurs when source b requires the output to the rd2 register
# (data processing instruction)
op.write(0)
bit4.write(1)
funct.write(1)
pp.run()
self.assertEqual(alusrcbd.read(), 1)
# test case 25 - occurs when source b requires an exdended immediate
op.write(0)
funct.write(63)
pp.run()
self.assertEqual(alusrcbd.read(), 0)
# test case 26 - occurs when source b requires an exdended immediate
op.write(1)
pp.run()
self.assertEqual(alusrcbd.read(), 0)
# alusd
# test case 27 - + operation
op.write(0)
funct.write(8)
pp.run()
self.assertEqual(alusd.read(), 0)
# test case 28 - + operation
op.write(1)
funct.write(25)
pp.run()
self.assertEqual(alusd.read(), 0)
# test case 29 - - operation
op.write(0)
funct.write(21)
pp.run()
self.assertEqual(alusd.read(), 1)
# test case 30 - and operation
op.write(0)
funct.write(32)
pp.run()
self.assertEqual(alusd.read(), 2)
# test case 31 - or operation
op.write(0)
funct.write(25)
pp.run()
self.assertEqual(alusd.read(), 3)
# test case 32 - xor operation
op.write(0)
funct.write(35)
pp.run()
self.assertEqual(alusd.read(), 4)
# test case 33 - return B
op.write(0)
funct.write(26)
pp.run()
self.assertEqual(alusd.read(), 6)
# test case 34 - * operation
op.write(0)
funct.write(1)
pp.run()
self.assertEqual(alusd.read(), 7)
# test case 35 - return 1
op.write(2)
pp.run()
self.assertEqual(alusd.read(), 15)
# aluflagwrd
# test case 36 - set c, v, n, z flags (cmp instructions or s bit set)
op.write(0)
funct.write(15)
pp.run()
self.assertEqual(aluflagwrd.read(), 1)
# test case 37 - flags will not be set
op.write(0)
funct.write(0)
pp.run()
self.assertEqual(aluflagwrd.read(), 0)
# test case 38 - flags will not be set
op.write(1)
pp.run()
self.assertEqual(aluflagwrd.read(), 0)
# memwrd
# test case 39 - allows data to be written to data memory (str instructions)
op.write(1)
funct.write(24)
pp.run()
self.assertEqual(memwrd.read(), 1)
# test case 40 - cannot write to data memory
op.write(0)
pp.run()
self.assertEqual(memwrd.read(), 0)
# regsrcd
# test case 41 - occurs when output of alu is feedback (ldr instructions)
op.write(1)
funct.write(25)
pp.run()
self.assertEqual(regsrcd.read(), 0)
# test case 42 - occurs when output of data memory is feedback
op.write(0)
pp.run()
self.assertEqual(regsrcd.read(), 1)
# wd3sd
# test case 43 - occurs when a bl is run
op.write(2)
funct.write(24)
pp.run()
self.assertEqual(wd3sd.read(), 1)
# test case 44 - occurs for all non bl instructions
op.write(0)
pp.run()
self.assertEqual(wd3sd.read(), 0)
def test_run(self):
"""
test's the alu's run function
"""
a = Bus(32)
b = Bus(32)
alus = Bus(4)
f = Bus(32)
c = Bus(1)
v = Bus(1)
n = Bus(1)
z = Bus(1)
# initialize alu
test_alu = Alu(a, b, alus, f, c, v, n, z)
# initialize inputs with values
a.write(5)
b.write(2)
# test case 3
alus.write(0)
test_alu.run()
self.assertEqual(f.read(), 7)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 0)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 0)
# test case 4
alus.write(1)
test_alu.run()
self.assertEqual(f.read(), 3)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 0)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 0)
# test case 5
alus.write(2)
test_alu.run()
self.assertEqual(f.read(), 0)
self.assertEqual(z.read(), 1)
self.assertEqual(n.read(), 0)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 0)
# test case 6
alus.write(3)
test_alu.run()
self.assertEqual(f.read(), 7)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 0)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 0)
# test case 7
alus.write(4)
test_alu.run()
self.assertEqual(f.read(), 7)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 0)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 0)
# test case 8
alus.write(5)
test_alu.run()
self.assertEqual(f.read(), 5)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 0)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 0)
# test case 9
alus.write(6)
test_alu.run()
self.assertEqual(f.read(), 2)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 0)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 0)
# test case 10
alus.write(7)
test_alu.run()
self.assertEqual(f.read(), 10)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 0)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 0)
# test case 11
alus.write(8)
test_alu.run()
self.assertEqual(f.read(), 1)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 0)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 0)
# test case 12
a.write(1)
b.write(2)
alus.write(1)
test_alu.run()
self.assertEqual(f.read(), 0xFFFFFFFF)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 1)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 0)
# test case 13
a.write(0x80000000)
b.write(0x80000000)
alus.write(0)
test_alu.run()
self.assertEqual(f.read(), 0)
self.assertEqual(z.read(), 1)
self.assertEqual(n.read(), 0)
self.assertEqual(c.read(), 1)
self.assertEqual(v.read(), 1)
# test case 14
a.write(0x7FFFFFFF)
b.write(0xFFFFFFFF)
alus.write(1)
test_alu.run()
self.assertEqual(f.read(), 0x80000000)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 1)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 1)
# test case 15
a.write(268435456)
b.write(9)
alus.write(7)
test_alu.run()
self.assertEqual(f.read(), 2415919104)
self.assertEqual(z.read(), 0)
self.assertEqual(n.read(), 1)
self.assertEqual(c.read(), 0)
self.assertEqual(v.read(), 1)
def test_on_falling_edge(self):
"Tests on_falling_edge method"
pc4m = Bus(32)
regwrm = Bus(1)
regsrcm = Bus(1)
wd3sm = Bus(1)
fm = Bus(32)
rdm = Bus(32)
ra3m = Bus(4)
clk = Bus(1)
pc4w = Bus(32)
regwrw = Bus(1)
regsrcw = Bus(1)
wd3sw = Bus(1)
fw = Bus(32)
rdw = Bus(32)
ra3w = Bus(4)
memwb = Memwb(pc4m, regwrm, regsrcm, wd3sm, fm, rdm, ra3m, clk, pc4w,
regwrw, regsrcw, wd3sw, fw, rdw, ra3w,
Latch_Type.FALLING_EDGE)
pc4m.write(4)
rdm.write(0x0A000002)
ra3m.write(5)
self.assertNotEqual(pc4m.read(), pc4w.read())
self.assertNotEqual(rdm.read(), rdw.read())
self.assertNotEqual(ra3m.read(), ra3w.read())
memwb.on_falling_edge()
self.assertEqual(pc4m.read(), pc4w.read())
self.assertEqual(rdm.read(), rdw.read())
self.assertEqual(ra3m.read(), ra3w.read())
def test_run(self):
"Tests the run method"
pc4d = Bus(32)
regwrd = Bus(1)
alusrcbd = Bus(1)
alusd = Bus(4)
aluflagwrd = Bus(1)
memwrd = Bus(1)
regsrcd = Bus(1)
wd3sd = Bus(1)
rd1d = Bus(32)
rd2d = Bus(32)
imm32d = Bus(32)
ra1d = Bus(4)
ra2d = Bus(4)
ra3d = Bus(4)
flush = Bus(1)
clk = Bus(1)
pc4e = Bus(32)
regwre = Bus(1)
alusrcbe = Bus(1)
aluse = Bus(4)
aluflagwre = Bus(1)
memwre = Bus(1)
regsrce = Bus(1)
wd3se = Bus(1)
rd1e = Bus(32)
rd2e = Bus(32)
imm32e = Bus(32)
ra1e = Bus(4)
ra2e = Bus(4)
ra3e = Bus(4)
idex = Idex(pc4d, regwrd, alusrcbd, alusd, aluflagwrd, memwrd, regsrcd,
wd3sd, rd1d, rd2d, imm32d, ra1d, ra2d, ra3d, flush, clk,
pc4e, regwre, alusrcbe, aluse, aluflagwre, memwre, regsrce,
wd3se, rd1e, rd2e, imm32e, ra1e, ra2e, ra3e)
aluflagwrd.write(1)
rd1d.write(0xE3A0A000)
ra3d.write(12)
idex.run()
self.assertNotEqual(aluflagwrd.read(), aluflagwre.read())
self.assertNotEqual(rd1d.read(), rd1e.read())
self.assertNotEqual(ra3d.read(), ra3e.read())
clk.write(1)
idex.run()
self.assertEqual(aluflagwrd.read(), aluflagwre.read())
self.assertEqual(rd1d.read(), rd1e.read())
self.assertEqual(ra3d.read(), ra3e.read())
clk.write(0)
idex.run()
flush.write(1)
clk.write(1)
idex.run()
self.assertNotEqual(aluflagwrd.read(), aluflagwre.read())
self.assertNotEqual(rd1d.read(), rd1e.read())
self.assertNotEqual(ra3d.read(), ra3e.read())
def test_run(self):
"Tests the run method"
pc4m = Bus(32)
regwrm = Bus(1)
regsrcm = Bus(1)
wd3sm = Bus(1)
fm = Bus(32)
rdm = Bus(32)
ra3m = Bus(4)
clk = Bus(1)
pc4w = Bus(32)
regwrw = Bus(1)
regsrcw = Bus(1)
wd3sw = Bus(1)
fw = Bus(32)
rdw = Bus(32)
ra3w = Bus(4)
memwb = Memwb(pc4m, regwrm, regsrcm, wd3sm, fm, rdm, ra3m, clk, pc4w,
regwrw, regsrcw, wd3sw, fw, rdw, ra3w)
pc4m.write(16)
wd3sm.write(1)
rdm.write(0xE3A0C004)
memwb.run()
self.assertNotEqual(pc4m.read(), pc4w.read())
self.assertNotEqual(wd3sm.read(), wd3sw.read())
self.assertNotEqual(rdm.read(), rdw.read())
clk.write(1)
memwb.run()
self.assertEqual(pc4m.read(), pc4w.read())
self.assertEqual(wd3sm.read(), wd3sw.read())
self.assertEqual(rdm.read(), rdw.read())
def test_run(self):
"Tests the signle cycle processors run method"
cond = Bus(4)
op = Bus(2)
funct = Bus(6)
rd = Bus(4)
bit4 = Bus(1)
c = Bus(1)
v = Bus(1)
n = Bus(1)
z = Bus(1)
pcsrc = Bus(2)
pcwr = Bus(1)
regsa = Bus(1)
regdst = Bus(2)
regwrs = Bus(2)
regwr = Bus(1)
exts = Bus(2)
alusrcb = Bus(1)
alus = Bus(4)
aluflagwr = Bus(1)
memwr = Bus(1)
regsrc = Bus(1)
wd3s = Bus(1)
# initialize single cycle controller
scc = ControllerSingleCycle(cond, op, funct, rd, bit4, c, v, n, z, pcsrc, pcwr, regsa,
regdst, regwrs, regwr, exts, alusrcb, alus, aluflagwr, memwr,
regsrc, wd3s)
# pcsrc tests
# test case 4 - occurs for banch instructions where condition is met
op.write(2)
cond.write(1)
scc.run()
self.assertEqual(pcsrc.read(), 0)
# test case 5 - occurs when a data processing instruction modifies pc
op.write(0)
rd.write(15)
scc.run()
self.assertEqual(pcsrc.read(), 2)
# test case 6 - for pc+4
op.write(1)
scc.run()
self.assertEqual(pcsrc.read(), 1)
# pcwr
# test case 7 - always a 1 for the single cycle processor
self.assertEqual(pcwr.read(), 1)
# regsa
# test case 8 - used to select Rn register (mul instruction)
op.write(0)
bit4.write(1)
funct.write(1)
scc.run()
self.assertEqual(regsa.read(), 0)
# test case 9 - used to select Rn register (data processing instuction)
op.write(1)
scc.run()
self.assertEqual(regsa.read(), 1)
# regdst
# test case 10 - used to select Rd register (str instruction)
op.write(1)
funct.write(24)
scc.run()
self.assertEqual(regdst.read(), 2)
# test case 11 - used to select Rm register (data processing instruction)
op.write(0)
bit4.write(1)
funct.write(0)
scc.run()
self.assertEqual(regdst.read(), 0)
# test case 12 - used to select Rm register (mul instruction)
op.write(2)
scc.run()
self.assertEqual(regdst.read(), 1)
# regwrs
# test cast 13 - used to select lr instruction (bl instruction)
op.write(2)
funct.write(16)
scc.run()
self.assertEqual(regwrs.read(), 2)
# test case 14 - used to select Rd register (data processing instruction)
op.write(0)
bit4.write(1)
funct.write(0)
scc.run()
self.assertEqual(regwrs.read(), 0)
# test case 15 - used to selcet Rd resister (mul instruction)
op.write(1)
scc.run()
self.assertEqual(regwrs.read(), 1)
# regwr
# test case 16 - occurs when an instruction writes back to the regfile
op.write(0)
funct.write(53)
scc.run()
self.assertEqual(regwr.read(), 0)
# test case 17 - occurs when an instruction writes back to the regfile
op.write(1)
funct.write(24)
scc.run()
self.assertEqual(regwr.read(), 0)
# test case 18 - occurs when an instruction writes back to the regfile
op.write(2)
funct.write(0b101100)
scc.run()
self.assertEqual(regwr.read(), 0)
# test case 19 - occurs when an instruction writes back to the regfile
funct.write(0b010000)
scc.run()
self.assertEqual(regwr.read(), 1)
# exts
# test case 20 - used for branch instruction
op.write(2)
scc.run()
self.assertEqual(exts.read(), 2)
# test case 21 - used for 12-bit immediate (ldr and str instructions)
op.write(1)
funct.write(25)
scc.run()
self.assertEqual(exts.read(), 1)
# test case 22 - used for 8-bit immediate (data processing immediate)
op.write(0)
scc.run()
self.assertEqual(exts.read(), 0)
# alusrcb
# test case 23 - occurs when source b requires the output to the rd2 register
# (data processing instruction)
op.write(0)
funct.write(28)
scc.run()
self.assertEqual(alusrcb.read(), 1)
# test case 24 - occurs when source b requires the output to the rd2 register
# (data processing instruction)
op.write(0)
bit4.write(1)
funct.write(1)
scc.run()
self.assertEqual(alusrcb.read(), 1)
# test case 25 - occurs when source b requires an exdended immediate
op.write(0)
funct.write(63)
scc.run()
self.assertEqual(alusrcb.read(), 0)
# test case 26 - occurs when source b requires an exdended immediate
op.write(1)
scc.run()
self.assertEqual(alusrcb.read(), 0)
# alus
# test case 27 - + operation
op.write(0)
funct.write(8)
scc.run()
self.assertEqual(alus.read(), 0)
# test case 28 - + operation
op.write(1)
funct.write(25)
scc.run()
self.assertEqual(alus.read(), 0)
# test case 30 - - operation
op.write(0)
funct.write(21)
scc.run()
self.assertEqual(alus.read(), 1)
# test case 31 - and operation
op.write(0)
funct.write(32)
scc.run()
self.assertEqual(alus.read(), 2)
# test case 32 - or operation
op.write(0)
funct.write(25)
scc.run()
self.assertEqual(alus.read(), 3)
# test case 33 - xor operation
op.write(0)
funct.write(35)
scc.run()
self.assertEqual(alus.read(), 4)
# test case 34 - return B
op.write(0)
funct.write(26)
scc.run()
self.assertEqual(alus.read(), 6)
# test case 35 - * operation
op.write(0)
funct.write(1)
scc.run()
self.assertEqual(alus.read(), 7)
# test case 36 - return 1
op.write(2)
scc.run()
self.assertEqual(alus.read(), 15)
# aluflagwr
# test case 37 - set c, v, n, z flags (cmp instructions or s bit set)
op.write(0)
funct.write(15)
scc.run()
self.assertEqual(aluflagwr.read(), 1)
# test case 39 - flags will not be set
op.write(0)
funct.write(0)
scc.run()
self.assertEqual(aluflagwr.read(), 0)
# test case 40 - flags will not be set
op.write(1)
scc.run()
self.assertEqual(aluflagwr.read(), 0)
# memwr
# test case 41 - allows data to be written to data memory (str instructions)
op.write(1)
funct.write(24)
scc.run()
self.assertEqual(memwr.read(), 1)
# test case 42 - cannot write to data memory
op.write(0)
scc.run()
self.assertEqual(memwr.read(), 0)
# regsrc
# test case 43 - occurs when output of alu is feedback (ldr instructions)
op.write(1)
funct.write(25)
scc.run()
self.assertEqual(regsrc.read(), 0)
# test case 44 - occurs when output of data memory is feedback
op.write(0)
scc.run()
self.assertEqual(regsrc.read(), 1)
# wd3s
# test case 45 - occurs when a bl is run
op.write(2)
funct.write(24)
scc.run()
self.assertEqual(wd3s.read(), 1)
# test case 46 - occurs for all non bl instructions
op.write(0)
scc.run()
self.assertEqual(wd3s.read(), 0)