def division_commands(reg_1: Register, reg_2: Register) -> [RegisterCommand]:
result: [RegisterCommand] = []
regs = register_manager.get_free_registers(3)
reg_3 = regs[0]
reg_4 = regs[1]
reg_5 = regs[2]
result.append(RegisterCommand(RegisterCommandType.SUB, reg_4, reg_4))
result.append(RegisterCommand(RegisterCommandType.JZERO, reg_1, 31))
result.append(RegisterCommand(RegisterCommandType.JZERO, reg_2, 30))
result.append(RegisterCommand(RegisterCommandType.SUB, reg_3, reg_3))
result.append(RegisterCommand(RegisterCommandType.INC, reg_3))
result.append(RegisterCommand(RegisterCommandType.COPY, reg_5, reg_1))
result.append(RegisterCommand(RegisterCommandType.INC, reg_1))
result.append(RegisterCommand(RegisterCommandType.SUB, reg_1, reg_2))
result.append(RegisterCommand(RegisterCommandType.JZERO, reg_1, 7))
result.append(RegisterCommand(RegisterCommandType.DEC, reg_1))
result.append(RegisterCommand(RegisterCommandType.JZERO, reg_1, 7))
result.append(RegisterCommand(RegisterCommandType.COPY, reg_1, reg_5))
result.append(RegisterCommand(RegisterCommandType.ADD, reg_2, reg_2))
result.append(RegisterCommand(RegisterCommandType.ADD, reg_3, reg_3))
result.append(RegisterCommand(RegisterCommandType.JUMP, -9))
result.append(RegisterCommand(RegisterCommandType.HALF, reg_3))
result.append(RegisterCommand(RegisterCommandType.HALF, reg_2))
result.append(RegisterCommand(RegisterCommandType.COPY, reg_1, reg_5))
result.append(RegisterCommand(RegisterCommandType.SUB, reg_2, reg_2))
result.append(RegisterCommand(RegisterCommandType.ADD, reg_4, reg_3))
result.append(RegisterCommand(RegisterCommandType.JZERO, reg_3, 12))
result.append(RegisterCommand(RegisterCommandType.COPY, reg_5, reg_1))
result.append(RegisterCommand(RegisterCommandType.INC, reg_1))
result.append(RegisterCommand(RegisterCommandType.SUB, reg_1, reg_2))
result.append(RegisterCommand(RegisterCommandType.JZERO, reg_1, 4))
result.append(RegisterCommand(RegisterCommandType.DEC, reg_1))
result.append(RegisterCommand(RegisterCommandType.ADD, reg_4, reg_3))
result.append(RegisterCommand(RegisterCommandType.JUMP, -7))
result.append(RegisterCommand(RegisterCommandType.COPY, reg_1, reg_5))
result.append(RegisterCommand(RegisterCommandType.HALF, reg_3))
result.append(RegisterCommand(RegisterCommandType.HALF, reg_2))
result.append(RegisterCommand(RegisterCommandType.JUMP, -10))
result.append(RegisterCommand(RegisterCommandType.COPY, reg_1, reg_4))
register_manager.release_registers(reg_2, reg_3, reg_4, reg_5)
return result
def make_number_commands(reg: Register, number: int, reg_help=None):
if not reg_help:
reg_help = register_manager.get_free_registers()
effect: [RegisterCommand] = [
RegisterCommand(RegisterCommandType.SUB, reg, reg),
RegisterCommand(RegisterCommandType.SUB, reg_help, reg_help),
RegisterCommand(RegisterCommandType.INC, reg_help)
]
res = 0
iq = 1
while 2 * iq < number:
iq = 2 * iq
effect.append(
RegisterCommand(RegisterCommandType.ADD, reg_help, reg_help))
while res != number:
while res + iq > number:
iq = iq / 2
effect.append(RegisterCommand(RegisterCommandType.HALF, reg_help))
res += iq
effect.append(RegisterCommand(RegisterCommandType.ADD, reg, reg_help))
register_manager.release_registers(reg_help)
return effect
def get_commands(self, setting: bool):
arr_tup = memory_manager.is_declared(self.identifier_type, self.data)
if self.identifier_type == IdentifierType.ARRAY_VALUE:
memory_idx = arr_tup.mem_fst + self.array_index - arr_tup.idx_fst
reg = register_manager.get_free_registers()
if setting:
result: [RegisterCommand
] = make_number_commands(memory_idx, reg)
register_manager.release_registers(reg)
arr_tup.initialize(self.array_index)
return result
else:
result: [RegisterCommand
] = make_number_commands(memory_idx, reg)
result.append(
RegisterCommand(RegisterCommandType.COPY,
register_manager.get_reg_a, reg))
result.append(RegisterCommand(RegisterCommandType.LOAD, reg))
register_manager.release_registers(reg)
return result
elif self.identifier_type == IdentifierType.ARRAY_VARIABLE:
reg = register_manager.get_free_registers()
reg_help = register_manager.get_free_registers()
idx_fst = arr_tup.idx_fst
mem_fst = arr_tup.mem_fst
if setting:
reg_number = register_manager.get_free_registers()
result: [RegisterCommand
] = RegisterCommand(RegisterCommandType.LOAD, reg,
reg_help)
result = concat_commands(
result, make_number_commands(reg_number, mem_fst,
reg_help))
result.append(
RegisterCommand(RegisterCommandType.ADD, reg, reg_number))
result = concat_commands(
result, make_number_commands(reg_number, idx_fst,
reg_help))
result.append(
RegisterCommand(RegisterCommandType.SUB, reg, reg_number))
register_manager.release_registers(reg_number, reg_help)
return result
else:
reg_a = register_manager.get_reg_a()
result: [RegisterCommand
] = RegisterCommand(RegisterCommandType.LOAD, reg_a,
reg_help)
result = concat_commands(
result, make_number_commands(reg, mem_fst, reg_help))
result.append(
RegisterCommand(RegisterCommandType.ADD, reg_a, reg))
result = concat_commands(
result, make_number_commands(reg, idx_fst, reg_help))
result.append(
RegisterCommand(RegisterCommandType.SUB, reg_a, reg))
result.append(RegisterCommand(RegisterCommandType.LOAD, reg))
return result
elif self.identifier_type == IdentifierType.VARIABLE:
reg = register_manager.get_free_registers()
mem = arr_tup.memory_idx
if setting:
res = make_number_commands(reg, mem)
register_manager.release_registers(reg)
arr_tup.initialize()
return res
else:
result = make_number_commands(reg, mem)
result.append(RegisterCommandType.COPY,
register_manager.get_reg_a(), reg)
result.append(RegisterCommandType.LOAD, reg)
return result
def subtraction_commands(reg_1: Register, reg_2: Register) -> [RegisterCommand]:
register_manager.release_registers(reg_2)
return [RegisterCommand(RegisterCommandType.SUB, reg_1, reg_2)]
def addition_commands(reg_1: Register, reg_2: Register) -> [RegisterCommand]:
register_manager.release_registers(reg_2)
return [RegisterCommand(RegisterCommandType.ADD, reg_1, reg_2)]