def gen_vhdl_axi(in_filename, out_filename):
if out_filename[-4:] != ".vhd":
raise ValueError("output filename is expected to have .vhd extension")
rdlc = RDLCompiler()
rdlc.compile_file(in_filename)
root = rdlc.elaborate()
walker = RDLWalker(unroll=True)
listener = HectareListener()
walker.walk(root, listener)
print("Parsing finished.")
vhdl_gen = HectareVhdlGen(listener.addrmaps[0], input_filename=in_filename)
s_pkg = vhdl_gen.generate_package()
s_vhdl = vhdl_gen.generate_string()
print("Generating {0} ...".format(out_filename))
out_file = open(out_filename, "w")
out_file.write(s_vhdl)
out_file.close()
if s_pkg is not None:
pkg_filename = out_filename.replace(".vhd", "_pkg.vhd")
print("Generating {0} ...".format(pkg_filename))
out_file = open(pkg_filename, "w")
out_file.write(s_pkg)
out_file.close()
def read_rdl(self, files=[]):
INFO("read_rdl: " + "Reading SystemRDL Files")
try:
#compile all the files provided
for input_file in files:
self.rdlc.compile_file(input_file)
self.root = self.rdlc.elaborate(
) #get the root of Tree in the RDL
except RDLCompileError:
sys.exit(1)
self.files = files
walker = RDLWalker(unroll=True)
walker.walk(self.root, self.listener)
self.listener.do_stats() #to process the information of SystemRDL file
def compile(self):
# Create an instance of the compiler
rdlc = RDLCompiler()
# Compile all the files provided
for input_file in self.input_files:
rdlc.compile_file(input_file)
# Elaborate the design
root = rdlc.elaborate()
# Traverse the register model!
walker = RDLWalker(unroll=True)
listener = MyModelPrintingListener()
walker.walk(root, listener)
def gen_c_header(in_filename, out_filename):
if out_filename[-2:] != ".h":
raise ValueError("output filename is expected to have .h extension")
rdlc = RDLCompiler()
rdlc.compile_file(in_filename)
root = rdlc.elaborate()
walker = RDLWalker(unroll=True)
listener = HectareListener()
walker.walk(root, listener)
print("Parsing finished.")
c_header_gen = HectareCHeaderGen(listener.addrmaps[0],
input_filename=in_filename)
s_header = c_header_gen.generate_string()
print("Generating {0} ...".format(out_filename))
out_file = open(out_filename, "w")
out_file.write(s_header)
out_file.close()
#parser.add_argument('--', type=int, help='Full (default) or Half duplex mode', required=False)
#parser.add_argument('--mc21', type=int, help='To remove', required=False)
#parser.add_argument('--servercamera', type=int, help='Camera number', required=False)
args = parser.parse_args()
#print(args)
rdlc = RDLCompiler()
try:
rdlc.compile_file(args.rdl)
root = rdlc.elaborate(args.chip)
except RDLCompileError:
sys.exit(1)
#sys.exit(10)
walker = RDLWalker(unroll=True)
golistener = RdlToGoCodeListener()
walker.walk(root, golistener)
print("//THIS FILE WAS AUTO GENERATED. PLEASE DO NOT EDIT")
print("package main")
print('func init() { addAddrMap("%s", %sRegisters[:]) }' %
(golistener.name, golistener.name))
print(golistener.r32)
def export(self, node: Node, path: str, **kwargs):
"""
Perform the export!
Parameters
----------
node: systemrdl.Node
Top-level node to export. Can be the top-level `RootNode` or any
internal `AddrmapNode`.
path: str
Output file.
export_as_package: bool
If True (Default), UVM register model is exported as a SystemVerilog
package. Package name is based on the output file name.
If False, register model is exported as an includable header.
reuse_class_definitions: bool
If True (Default), exporter attempts to re-use class definitions
where possible. Class names are based on the lexical scope of the
original SystemRDL definitions.
If False, class definitions are not reused. Class names are based on
the instance's hierarchical path.
use_uvm_factory: bool
If True, class definitions and class instances are created using the
UVM factory.
If False (Default), UVM factory is disabled. Classes are created
directly via new() constructors.
"""
export_as_package = kwargs.pop("export_as_package", True)
use_uvm_factory = kwargs.pop("use_uvm_factory", False)
self.reuse_class_definitions = kwargs.pop("reuse_class_definitions", True)
# Check for stray kwargs
if kwargs:
raise TypeError("got an unexpected keyword argument '%s'" % list(kwargs.keys())[0])
# If it is the root node, skip to top addrmap
if isinstance(node, RootNode):
node = node.top
self.top = node
if isinstance(node, AddrmapNode) and node.get_property('bridge'):
node.env.msg.warning(
"UVM RAL generator does not have proper support for bridge addmaps yet. The 'bridge' property will be ignored.",
node.inst.property_src_ref.get('bridge', node.inst.inst_src_ref)
)
# First, traverse the model and collect some information
self.bus_width_db = {}
RDLWalker().walk(self.top, PreExportListener(self))
context = {
'top_node': node,
'RegNode': RegNode,
'RegfileNode': RegfileNode,
'AddrmapNode': AddrmapNode,
'MemNode': MemNode,
'AddressableNode': AddressableNode,
'isinstance': isinstance,
'class_needs_definition': self._class_needs_definition,
'get_class_name': self._get_class_name,
'get_class_friendly_name': self._get_class_friendly_name,
'get_inst_name': self._get_inst_name,
'get_field_access': self._get_field_access,
'get_array_address_offset_expr': self._get_array_address_offset_expr,
'get_endianness': self._get_endianness,
'get_bus_width': self._get_bus_width,
'get_mem_access': self._get_mem_access,
'roundup_to': self._roundup_to,
'roundup_pow2': self._roundup_pow2,
'use_uvm_factory': use_uvm_factory,
}
context.update(self.user_template_context)
if export_as_package:
context['package_name'] = self._get_package_name(path)
template = self.jj_env.get_template("top_pkg.sv")
else:
context['include_guard'] = self._get_include_guard(path)
template = self.jj_env.get_template("top_include.svh")
stream = template.stream(context)
stream.dump(path)
from systemrdl import RDLCompiler, RDLCompileError, RDLWalker
from systemrdl.messages import FileSourceRef
# Create a compiler session, and an importer attached to it
rdlc = RDLCompiler()
json_importer = JSONImporter(rdlc)
# import each JSON file provided from the command line
input_files = sys.argv[1:]
try:
for input_file in input_files:
# compile or import based on the file extension
ext = os.path.splitext(input_file)[1]
if ext == ".rdl":
rdlc.compile_file(input_file)
elif ext == ".json":
json_importer.import_file(input_file)
else:
rdlc.msg.fatal("Unknown file extension: %s" % ext,
FileSourceRef(input_file))
# Elaborate when done
root = rdlc.elaborate()
except RDLCompileError:
sys.exit(1)
# Lets use the first example's listener to display the imported model
from print_hierarchy import MyModelPrintingListener
walker = RDLWalker()
listener = MyModelPrintingListener()
walker.walk(root, listener)
def do_export(self, top_node: AddrmapNode,
options: 'argparse.Namespace') -> None:
hex_digits = math.ceil(top_node.total_size.bit_length() / 4)
walker = RDLWalker(unroll=options.unroll)
listener = DumpListener(hex_digits, options.unroll)
walker.walk(top_node, listener)