def check_ld_indexed_addr_immediate(self, op_codes, index_register):
# given
operand = random_byte()
immediate_value = random_byte()
self.processor.index_registers[index_register] = 0x1000
self.given_next_instruction_is(op_codes[0], op_codes[1], operand, immediate_value)
# when
self.processor.execute()
# then
assert_equals(self.memory[0xffff & (0x1000 + to_signed(operand))], immediate_value)
def test_ld_a_ext_addr(self):
# given
little_endian_address = [random_byte(), random_byte()]
self.given_next_instruction_is(0x3a, little_endian_address[0], little_endian_address[1])
memory_value = random_byte()
self.memory[big_endian_value(little_endian_address)] = memory_value
# when
self.processor.execute()
# then
self.assert_pc_address().equals(0x0003)
assert_equals(self.processor.main_registers['a'], memory_value)
def test_ld_ext_addr_from_a(self):
# given
register_value = random_byte()
self.given_register_contains_value('a', register_value)
little_endian_address = [random_byte(), random_byte()]
self.given_next_instruction_is(0x32, little_endian_address[0], little_endian_address[1])
# when
self.processor.execute()
# then
self.assert_pc_address().equals(0x0003)
assert_equals(self.memory[big_endian_value(little_endian_address)], register_value)
def check_ld_indexed_addr_immediate(self, op_codes, index_register):
# given
operand = random_byte()
immediate_value = random_byte()
self.processor.index_registers[index_register] = 0x1000
self.given_next_instruction_is(op_codes[0], op_codes[1], operand,
immediate_value)
# when
self.processor.execute()
# then
assert_equals(self.memory[0xffff & (0x1000 + to_signed(operand))],
immediate_value)
def test_ld_a_ext_addr(self):
# given
little_endian_address = [random_byte(), random_byte()]
self.given_next_instruction_is(0x3a, little_endian_address[0],
little_endian_address[1])
memory_value = random_byte()
self.memory[big_endian_value(little_endian_address)] = memory_value
# when
self.processor.execute()
# then
self.assert_pc_address().equals(0x0003)
assert_equals(self.processor.main_registers['a'], memory_value)
def test_ld_ext_addr_from_a(self):
# given
register_value = random_byte()
self.given_register_contains_value('a', register_value)
little_endian_address = [random_byte(), random_byte()]
self.given_next_instruction_is(0x32, little_endian_address[0],
little_endian_address[1])
# when
self.processor.execute()
# then
self.assert_pc_address().equals(0x0003)
assert_equals(self.memory[big_endian_value(little_endian_address)],
register_value)
def check_ld_16reg_immediate(self, op_codes, register_pair):
# given
little_endian_address = [random_byte(), random_byte()]
self.given_next_instruction_is(op_codes, little_endian_address)
# when
self.processor.execute()
# then
if register_pair == 'ix':
assert_equals(self.processor.index_registers['ix'], big_endian_value(little_endian_address))
elif register_pair == 'iy':
assert_equals(self.processor.index_registers['iy'], big_endian_value(little_endian_address))
elif register_pair == 'sp':
assert_equals(self.processor.special_registers['sp'], big_endian_value(little_endian_address))
else:
assert_equals(self.processor.main_registers[register_pair[0]], little_endian_address[1])
assert_equals(self.processor.main_registers[register_pair[1]], little_endian_address[0])
def test_ld_indexed_reg_from_reg(self):
operations = [([0xdd, 0x77], 'ix', 'a'), ([0xfd, 0x77], 'iy', 'a'),
([0xdd, 0x70], 'ix', 'b'), ([0xfd, 0x70], 'iy', 'b'),
([0xdd, 0x71], 'ix', 'c'), ([0xfd, 0x71], 'iy', 'c'),
([0xdd, 0x72], 'ix', 'd'), ([0xfd, 0x72], 'iy', 'd'),
([0xdd, 0x73], 'ix', 'e'), ([0xfd, 0x73], 'iy', 'e'),
([0xdd, 0x74], 'ix', 'h'), ([0xfd, 0x74], 'iy', 'h'),
([0xdd, 0x75], 'ix', 'l'), ([0xfd, 0x75], 'iy', 'l')]
for op_codes, destination_index_register, source_register in operations:
yield self.check_ld_indexed_reg_from_reg, op_codes, destination_index_register, \
source_register, random_byte()
def check_push_without_wraparound(self, op_codes, register_pair):
lsb = random_byte()
msb = random_byte()
# given
if register_pair == 'ix' or register_pair == 'iy':
self.given_register_contains_value(register_pair, big_endian_value([lsb, msb]))
else:
self.given_register_contains_value(register_pair[0], msb)
self.given_register_contains_value(register_pair[1], lsb)
self.given_stack_pointer_is(0xffff)
self.given_next_instruction_is(op_codes)
# when
self.processor.execute()
# then
assert_equals(self.processor.special_registers['sp'], 0xfffd)
assert_equals(self.memory[0xfffe], msb)
assert_equals(self.memory[0xfffd], lsb)
def check_ld_16reg_immediate(self, op_codes, register_pair):
# given
little_endian_address = [random_byte(), random_byte()]
self.given_next_instruction_is(op_codes, little_endian_address)
# when
self.processor.execute()
# then
if register_pair == 'ix':
assert_equals(self.processor.index_registers['ix'],
big_endian_value(little_endian_address))
elif register_pair == 'iy':
assert_equals(self.processor.index_registers['iy'],
big_endian_value(little_endian_address))
elif register_pair == 'sp':
assert_equals(self.processor.special_registers['sp'],
big_endian_value(little_endian_address))
else:
assert_equals(self.processor.main_registers[register_pair[0]],
little_endian_address[1])
assert_equals(self.processor.main_registers[register_pair[1]],
little_endian_address[0])
def check_pop_without_workaround(self, op_codes, register_pair):
# given
msb = random_byte()
lsb = random_byte()
self.memory[0xfff0] = lsb
self.memory[0xfff1] = msb
self.given_stack_pointer_is(0xfff0)
self.given_next_instruction_is(op_codes)
# when
self.processor.execute()
# then
assert_equals(self.processor.special_registers['sp'], 0xfff2)
if register_pair == 'ix' or register_pair == 'iy':
assert_equals(self.processor.index_registers[register_pair], big_endian_value([lsb, msb]))
else:
assert_equals(self.processor.main_registers[register_pair[0]], msb)
assert_equals(self.processor.main_registers[register_pair[1]], lsb)
def check_push_without_wraparound(self, op_codes, register_pair):
lsb = random_byte()
msb = random_byte()
# given
if register_pair == 'ix' or register_pair == 'iy':
self.given_register_contains_value(register_pair,
big_endian_value([lsb, msb]))
else:
self.given_register_contains_value(register_pair[0], msb)
self.given_register_contains_value(register_pair[1], lsb)
self.given_stack_pointer_is(0xffff)
self.given_next_instruction_is(op_codes)
# when
self.processor.execute()
# then
assert_equals(self.processor.special_registers['sp'], 0xfffd)
assert_equals(self.memory[0xfffe], msb)
assert_equals(self.memory[0xfffd], lsb)
def check_pop_without_workaround(self, op_codes, register_pair):
# given
msb = random_byte()
lsb = random_byte()
self.memory[0xfff0] = lsb
self.memory[0xfff1] = msb
self.given_stack_pointer_is(0xfff0)
self.given_next_instruction_is(op_codes)
# when
self.processor.execute()
# then
assert_equals(self.processor.special_registers['sp'], 0xfff2)
if register_pair == 'ix' or register_pair == 'iy':
assert_equals(self.processor.index_registers[register_pair],
big_endian_value([lsb, msb]))
else:
assert_equals(self.processor.main_registers[register_pair[0]], msb)
assert_equals(self.processor.main_registers[register_pair[1]], lsb)
def check_ld_reg_indexed_addr(self, op_codes, destination_register, index_register, operand):
# given
self.given_next_instruction_is(op_codes[0], op_codes[1], operand)
self.given_register_contains_value(index_register, 0x1000)
referenced_address = 0x1000 + to_signed(operand)
address_value = random_byte()
self.memory[referenced_address] = address_value
# when
self.processor.execute()
# then
self.assert_pc_address().equals(0x0003)
assert_equals(self.processor.main_registers[destination_register], address_value)
def check_ld_indexed_reg_from_reg(self, op_codes, destination_index_register, source_register, operand):
# given
self.given_next_instruction_is(op_codes[0], op_codes[1], operand)
register_value = random_byte()
self.given_register_contains_value(source_register, register_value)
self.given_register_contains_value(destination_index_register, 0x1000)
# when
self.processor.execute()
# then
self.assert_pc_address().equals(0x0003)
referenced_address = 0x1000 + to_signed(operand)
assert_equals(self.memory[referenced_address], register_value)
def check_ld_reg_indexed_addr(self, op_codes, destination_register,
index_register, operand):
# given
self.given_next_instruction_is(op_codes[0], op_codes[1], operand)
self.given_register_contains_value(index_register, 0x1000)
referenced_address = 0x1000 + to_signed(operand)
address_value = random_byte()
self.memory[referenced_address] = address_value
# when
self.processor.execute()
# then
self.assert_pc_address().equals(0x0003)
assert_equals(self.processor.main_registers[destination_register],
address_value)
def check_ld_indexed_reg_from_reg(self, op_codes,
destination_index_register,
source_register, operand):
# given
self.given_next_instruction_is(op_codes[0], op_codes[1], operand)
register_value = random_byte()
self.given_register_contains_value(source_register, register_value)
self.given_register_contains_value(destination_index_register, 0x1000)
# when
self.processor.execute()
# then
self.assert_pc_address().equals(0x0003)
referenced_address = 0x1000 + to_signed(operand)
assert_equals(self.memory[referenced_address], register_value)
def test_ld_indexed_reg_from_reg(self):
operations = [
([0xdd, 0x77], 'ix', 'a'),
([0xfd, 0x77], 'iy', 'a'),
([0xdd, 0x70], 'ix', 'b'),
([0xfd, 0x70], 'iy', 'b'),
([0xdd, 0x71], 'ix', 'c'),
([0xfd, 0x71], 'iy', 'c'),
([0xdd, 0x72], 'ix', 'd'),
([0xfd, 0x72], 'iy', 'd'),
([0xdd, 0x73], 'ix', 'e'),
([0xfd, 0x73], 'iy', 'e'),
([0xdd, 0x74], 'ix', 'h'),
([0xfd, 0x74], 'iy', 'h'),
([0xdd, 0x75], 'ix', 'l'),
([0xfd, 0x75], 'iy', 'l')
]
for op_codes, destination_index_register, source_register in operations:
yield self.check_ld_indexed_reg_from_reg, op_codes, destination_index_register, \
source_register, random_byte()
def test_ld_reg_indexed_addr(self):
operations = [([0xdd, 0x7e], 'a', 'ix'), ([0xfd, 0x7e], 'a', 'iy'),
([0xdd, 0x46], 'b', 'ix'), ([0xfd, 0x46], 'b', 'iy'),
([0xdd, 0x4e], 'c', 'ix'), ([0xfd, 0x4e], 'c', 'iy'),
([0xdd, 0x56], 'd', 'ix'), ([0xfd, 0x56], 'd', 'iy'),
([0xdd, 0x5e], 'e', 'ix'), ([0xfd, 0x5e], 'e', 'iy'),
([0xdd, 0x66], 'h', 'ix'), ([0xfd, 0x66], 'h', 'iy'),
([0xdd, 0x6e], 'l', 'ix'), ([0xfd, 0x6e], 'l', 'iy')]
for op_codes, destination_register, index_register in operations:
yield self.check_ld_reg_indexed_addr, op_codes, destination_register, index_register, random_byte(
)
def test_ld_reg_indexed_addr(self):
operations = [
([0xdd, 0x7e], 'a', 'ix'), ([0xfd, 0x7e], 'a', 'iy'),
([0xdd, 0x46], 'b', 'ix'), ([0xfd, 0x46], 'b', 'iy'),
([0xdd, 0x4e], 'c', 'ix'), ([0xfd, 0x4e], 'c', 'iy'),
([0xdd, 0x56], 'd', 'ix'), ([0xfd, 0x56], 'd', 'iy'),
([0xdd, 0x5e], 'e', 'ix'), ([0xfd, 0x5e], 'e', 'iy'),
([0xdd, 0x66], 'h', 'ix'), ([0xfd, 0x66], 'h', 'iy'),
([0xdd, 0x6e], 'l', 'ix'), ([0xfd, 0x6e], 'l', 'iy')
]
for op_codes, destination_register, index_register in operations:
yield self.check_ld_reg_indexed_addr, op_codes, destination_register, index_register, random_byte()
