def __init__(self):
ScanBasic.__init__(self)
self.patterns = {
#| Tool Version : Vivado v.2014.4 (win64) Build
"001 Version" : re.compile("^\| Tool Version :\s+(.*?)\s+Build"),
"002 Device" : [re.compile("^\| Device\s+:\s+(\S+)"),
],
#| Device : xc7a100t
# -----
"003 Register" : re.compile("Slice Registers\s+\|\s+(\S+)"),
#| Slice Registers | 832 | 0 | 126800 | 0.65 |
"004 LUT" : re.compile("\| Slice LUTs\s+\|\s+(\S+)"),
#| Slice LUTs | 810 | 0 | 63400 | 1.27 |
#| Bonded IOB | 135 | 0 | 170 | 79.41 |
"005 IO": re.compile("^\| Bonded IOB\s+\|\s+(\S+)"),
#| Slice | 314 | 0 | 15850 | 1.98 |
"006 Slice":re.compile("^\| Slice\s+\|\s+(\S+)"),
#| Block RAM Tile | 0 | 0 | 135 | 0.00 |
#| RAMB36/FIFO* | 0 | 0 | 135 | 0.00 |
#| RAMB18 | 0 | 0 | 270 | 0.00 |
"007 Block_RAM":[re.compile("\| Block RAM Tile \|\s+(\S+)"),
re.compile("\| RAMB36/FIFO\* \|\s+(\S+)"),
re.compile("\| RAMB18 \|\s+(\S+)"),
],
#| DSPs | 0 | 0 | 240 | 0.00 |
"008 Dsp":[re.compile("\| DSPs\s+\|\s+(\S+)"),
],
}
self.reset()
def __init__(self):
ScanBasic.__init__(self)
self.patterns = {
"002 ngdbuild" : re.compile("^([\.\d]+)\s+,\s+\S+ngdbuild\s+"),
"003 map" : re.compile("^([\.\d]+)\s+,\s+\S+map\s+"),
"004 par" : re.compile("^([\.\d]+)\s+,\s+\S+par\s+"),
"005 trce" : re.compile("^([\.\d]+)\s+,\s+\S+trce\s+")
}
self.reset()
def __init__(self):
ScanBasic.__init__(self)
self.patterns = {
"001 Device": [
re.compile("^Target Device\s+:\s+(\S+)"),
re.compile("^Target Package\s+:\s+(\S+)"),
re.compile("^Target Speed\s+:\s+-(\S+)")
],
# Target Device : xc6slx25t
# Target Package : csg324
# Target Speed : -4
# -----
"002 Register":
re.compile("^Number of Slice Registers:\s+(\S+)"),
"003 LUT":
re.compile("^Number of Slice LUTs:\s+(\S+)"),
# Number of Slice Registers: 1,097 out of 30,064 3%
# Number of Slice LUTs: 967 out of 15,032 6%
#Number of bonded IOBs: 126 out of 170 74%
"004 IO":
re.compile("Number of bonded IOBs:\s+(\S+)"),
# Number of occupied Slices: 508 out of 3,758 13%
"005 Slice":
re.compile("Number of occupied Slices:\s+(\S+)"),
#Number used as Memory: 27 out of 3,664 1%
"006 Dist_RAMs":
re.compile("Number used as Memory:\s+(\S+)"),
# Number of RAMB16BWERs: 0 out of 52 0%
#Number of RAMB8BWERs: 1 out of 104 1%
#Number of RAMB36E1/FIFO36E1s: 0 out of 135 0%
#Number of RAMB18E1/FIFO18E1s: 0 out of 270 0%
"007 Block_RAM": [
re.compile("Number of RAMB16BWERs:\s+(\S+)"),
re.compile("Number of RAMB8BWERs:\s+(\S+)"),
re.compile("Number of RAMB36E1/FIFO36E1s:\s+(\S+)"),
re.compile("Number of RAMB18E1/FIFO18E1s:\s+(\S+)"),
],
#Number of DSP48A1s: 0 out of 38 0%
#Number of DSP48E1s: 0 out of 240 0%
"008 Dsp": [
re.compile("Number\s+of\s+DSP48A1s:\s+(\S+)"),
re.compile("Number\s+of\s+DSP48E1s:\s+(\S+)")
],
#Number of MMCME2_ADVs: 1 out of 10 10%
#Number of PLLE2_ADVs: 0 out of 6 0%
#Number of DCM/DCM_CLKGENs: 0 out of 4 0%
#Number of MMCM_ADVs: 0 out of 6 0%
"009 PLL": [
re.compile("Number of MMCME2_ADVs:\s+(\S+)"),
re.compile("Number of PLLE2_ADVs:\s+(\S+)"),
re.compile("Number of DCM/DCM_CLKGENs:\s+(\S+)"),
re.compile("Number of MMCM_ADVs:\s+(\S+)")
],
}
self.reset()
def __init__(self):
ScanBasic.__init__(self)
self.patterns = {
"002 Device" : re.compile("^;\s+Device\s+;\s+(\S+)"),
"003 LE" : re.compile("^;\s+Total logic elements\s+;\s+(\S+)"),
#; -- Combinational with no register ; 560 ;
#; -- Combinational with a register ; 797 ;
"004 LUT" : [
re.compile("^;\s+--\s+Combinational with no register\s+;\s+(\S+)"),
re.compile("^;\s+--\s+Combinational with a register\s+;\s+(\S+)")],
# ; Combinational ALUT usage for logic ; 1,057 ; ;
# ; Combinational ALUT usage for route-throughs ; 185 ; ;
# ; Memory ALUT usage ; 33 ; ;
# ; ALUTs Used ; 315 / 99,280 ( < 1 % ) ;
"005 ALUT": [re.compile("^;\s+Combinational ALUT usage for logic\s+;\s+(\S+)\s+;\s+;"),
#re.compile("^;\s+Combinational ALUT usage for route-throughs\s+;\s+(\S+)\s+;\s+;"),
re.compile("^;\s+Memory ALUT usage\s+;\s+(\S+)\s+;\s+;"),
re.compile("^;\s+ALUTs Used\s+;\s+(\S+)\s+;\s+;")],
"006 IO" : re.compile("^;\s+Total pins\s+;\s+(\S+)"),
"007 Memory" : re.compile("^;\s+Total memory bits\s+;\s+(\S+)"),
"008 DSP" : [re.compile("^;\s+Embedded Multiplier 9-bit elements\s+;\s+(\S+)"),
re.compile("^;\s+DSP block 18-bit elements\s+;\s+(\S+)"),
re.compile("^;\s+Total DSP Blocks\s+;\s+(\S+)")],
#; Logic utilization (in ALMs) ; 702 / 9,430 ( 7 % ) ;
#; ALMs: partially or completely used ; 226 / 49,640 ( < 1 % ) ;
"009 ALMs":[re.compile(r"^;\s+Logic utilization \(in ALMs\)\s+;\s+(\S+)"),
re.compile(r"^;\s+ALMs:\s+partially or completely used\s+;\s+(\S+)")],
#; Logic utilization (ALMs needed / total ALMs on device) ; 188 / 29,080 ; < 1 % ;
#; Logic utilization ; 356 / 64,000 ( < 1 % ) ;
"010 LogicUtil":[re.compile("^;\s+Logic utilization \(ALMs needed / total ALMs on device\)\s+;\s+(\S+)"),
re.compile("^;\s+Logic utilization\s+;\s+(\S+)")],
#; Total MLAB memory bits ; 0 ; ;
"011 Dist_RAMs":re.compile("^;\s+Total MLAB memory bits\s+;\s+(\S+)"),
"012 PLL" : re.compile("^;\s+Total PLLs\s+;\s+(\S+)"),
# +------------------------------------+-------------------------------------------+
# ; Fitter Status ; Successful - Tue Dec 18 12:09:26 2012 ;
# ; Quartus II 32-bit Version ; 12.1 Build 177 11/07/2012 SJ Full Version ;
# ; Revision Name ; TopLevel ;
# ; Top-level Entity Name ; TopLevel ;
# ; Family ; Cyclone IV E ;
# ; Device ; EP4CE22F17C6 ;
# ; Timing Models ; Final ;
# ; Total logic elements ; 16,172 / 22,320 ( 72 % ) ;
# ; Total combinational functions ; 15,257 / 22,320 ( 68 % ) ;
# ; Dedicated logic registers ; 4,873 / 22,320 ( 22 % ) ;
# ; Total registers ; 4873 ;
# ; Total pins ; 93 / 154 ( 60 % ) ;
# ; Total virtual pins ; 0 ;
# ; Total memory bits ; 272,128 / 608,256 ( 45 % ) ;
# ; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
# ; Total PLLs ; 1 / 4 ( 25 % ) ;
# +------------------------------------+-------------------------------------------+
"013 LAB" : re.compile("^; Total LABs: partially or completely used\s+;\s+(\S+)"),
"014 M9K" : [re.compile("^; M9Ks\s+;\s+(\S+)"),
re.compile("^M9K blocks\s+;\s+(\S)")],
"015 M10K":re.compile("^;\s+M10K blocks\s+;\s+(\S+)"),
"016 M144K":re.compile("^;\s+M144K blocks\s+;\s+(\S+)"),
"017 Register" : re.compile("^;\s+Total registers\s+;\s+(\S+)"),
# ; Total LABs: partially or completely used ; 1,118 / 1,395 ( 80 % ) ;
# ; M9Ks ; 44 / 66 ( 67 % ) ;
"stop" : re.compile("^;\s+Input Pins"),
#"101 FitPeakMem" : re.compile("^Info: Peak virtual memory:\s+(\S+)"),
#"102 FitCPUTime" : re.compile("^Info: Total CPU time[^:]+:\s+(\S+)")
# Info: Peak virtual memory: 408 megabytes
# Info: Total CPU time (on all processors): 00:00:10
}
self.reset()
def __init__(self):
ScanBasic.__init__(self)
self.patterns = {
"001 edif2ngd" : re.compile("^([\.\d]+)\s+,\s+\S+edif2ngd\s+"),
"002 ngdbuild" : re.compile("^([\.\d]+)\s+,\s+\S+ngdbuild\s+"),
"003 map" : re.compile("^([\.\d]+)\s+,\s+\S+map\s+"),
"004 par" : re.compile("^([\.\d]+)\s+,\s+\S+par\s+"),
"005 trce" : re.compile("^([\.\d]+)\s+,\s+\S+trce\s+")
}
self.patterns_srr = {
#Process took 0h:00m:01s realtime, 0h:00m:01s cputime
"001 srr_time" : re.compile("^Process\s+took\s+(.+)\s+realtime,\s+(.+)\s+cputime NO use"), # this is useless now( according to jeffrey ye)
#CCU2D: 88 #synthesis
#CCU2D => 85 #lse
"002 CCU_lse" : re.compile("^CCU.*?\s+(\d+)"),
#Peak Memory Usage: 125.008 MB
# This is the old one-- "003 SynPeakMem":re.compile("^Peak\sMemory\sUsage:\s+([\d.]+)"),
#At Mapper Exit (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:30s; Memory used current: 69MB peak: 241MB)
#"003 SynPeakMem":re.compile("^At\sMapper\sExit.+?peak:\s([\d.]+)MB"),
"003 SynPeakMem":re.compile("Memory used current:.+?peak:\s([\d.]+)MB"),
#Elapsed CPU time for LSE flow : 7.301 secs
"004 lse_CPU_Time":re.compile("^Elapsed\s+CPU\s+time\s+for\s+LSE\s+flow\s+:\s+([\d.]+)"),
"005 PostLSEClk_PostLSEFmax":re.compile('''create_clock\s+-period\s+\S+\s+-name\s+
\S+\s+
\[get_nets\s+(\S+?)\]\s+
[\.\d]+\s+MHz\s+
([\.\d]+)\s+MHz''', re.VERBOSE | re.I),
#Peak Memory Usage: 51.152 MB
"007 LsePeakMem":re.compile("^Peak\sMemory\sUsage:\s+([\d.]+)"),
#At c_hdl Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 3MB peak: 4MB)
"008 at_c_hdl":re.compile("^At c_hdl Exit \(Real Time elapsed\s+(.+);\s+CPU Time elapsed\s+(.+);"),
#At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)
"009 at_syn_nfilter":re.compile("^At syn_nfilter Exit \(Real Time elapsed\s+(.+);\s+CPU Time elapsed\s+(.+);"),
#At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 88MB peak: 153MB)
"010 pre_opt_map":re.compile("^At Mapper Exit \(Real Time elapsed\s+(.+);\s+CPU Time elapsed\s+(.+);"),
}
self.patterns_mrp = {
# Total CPU Time: 3 secs
"001 mrp_CPU_Time": re.compile("Total\s+CPU\s+Time:\s+(.+)"),
# Total REAL Time: 4 secs
"002 mrp_REAL_Time": re.compile("Total\s+REAL\s+Time:\s+(.+)")
}
self.patterns_par = {
#Total CPU time 1 mins 41 secs
"001 par_CPU_Time": re.compile("Total\s+CPU\s+time\s+to\s+completion:?\s+(.+)"),
#Total REAL time: 1 mins 42 secs
"002 par_REAL_Time": re.compile("Total\s+REAL\s+time\s+to\s+completion:\s+(.+)"),
"003 Complete" : re.compile("All signals are completely routed."),
"004 Par_Done" : re.compile("par done!"),
#PAR peak memory usage: 59.777 Mbytes
"005 ParPeakMem":re.compile("PAR\s+peak\s+memory\s+usage:\s+([\d \.]+)\s+Mbytes")
}
self.srr_data = {
'srr_Real_time':'NA',
'srr_Cpu_time' : 'NA',
'CCU_lse':'NA',
'SynPeakMem':'NA',
'lse_CPU_Time':'NA',
'PostLSEClk':'NA',
'PostLSEFmax':'NA',
'LsePeakMem':'NA'
}
self.mrp_time = {}
for key in self.patterns_mrp.keys():
key = key.split()[1]
self.mrp_time[key] = 'NA'
self.par_data={}
for key in self.patterns_par.keys():
key = key.split()[1]
self.par_data[key] = 'NA'
self.reset()
def __init__(self):
ScanBasic.__init__(self)
self.patterns = {
"001 Version" : re.compile("^Mapper:.+version:\s+(.+)"),
"002 Device" : [re.compile("^Target Device:\s+(\S+)"),
re.compile("^Target Performance:\s+(\S+)")],
# Target Device: LFEC6EFPBGA256
# Target Performance: 5
# Mapper: ep5g00, version: Diamond Version 2.1.0.56
# -----
"003 Register" : [re.compile("^Number of registers:\s+(\d+)"),
re.compile("^Number of PFU registers:\s+(\d+)")],
"004 Slice" : re.compile("^Number of SLICEs:\s+(\d+)"),
"005 LUT" : [re.compile("^Total number of LUT4s:\s+(\d+)"),
re.compile("^Number of LUT4s:\s+(\d+)")],
# Number of registers: 728
# Number of SLICEs: 656 out of 3072 (21%)
# Total number of LUT4s: 774
#Number of LUT4s: 57172 out of 92016
# -----
"006 IO" : [re.compile("^Number of PIO sites used:\s+(\d+)"),
re.compile("^Number of external PIOs:\s+(\d+)")],
"007 EBR" : re.compile("^Number of block RAMs:\s+(\d+)"),
"008 DRAM" : [re.compile("^Number of distributed RAM:\s+(\d+)"),re.compile("^Number used as distributed RAM:\s+(\d+)")],
# Number of PIO sites used: 143 out of 195 (73%)
# Number of block RAMs: 3 out of 10 (30%)
# Number of distributed RAM: 16 (32 LUT4s)
# -----
"009 DSP" : re.compile("^Number of Used DSP Sites:\s+(\d+)"),
"010 DSP_MULT" : re.compile("^Number of Used DSP MULT Sites:\s+(\d+)"),
"011 DSP_ALU" : re.compile("^Number of Used DSP ALU Sites:\s+(\d+)"),
# Number of Used DSP Sites: 0 out of 48 (0 %)
# Number of Used DSP MULT Sites: 0 out of 48 (0 %)
# Number of Used DSP ALU Sites: 0 out of 24 (0 %)
# -----
"012 PCS" : re.compile("^Number of PCS \(SerDes\):\s+(\d+)"),
# Number of PCS (SerDes): 0 out of 1 (0%) with bonded PIO sites
#Number of distributed RAM: 0 (0 LUT4s)
"013 distributed_RAM" : [re.compile("^Number of distributed RAM:\s+(\d+)"), re.compile("^Number used as distributed RAM:\s+(\d+)")],
#Number of ripple logic: 2598 (5196 LUT4s)
"014 CCU" : [re.compile("^Number of ripple logic:\s+(\d+)"),re.compile("^Number used as ripple logic:\s+(\d+)")],
### add dsp detail
"015 MULT18X18D" : re.compile("^MULT18X18D\s+(\d+)"),
"016 MULT9X9D" : re.compile("^MULT9X9D\s+(\d+)"),
"017 ALU54B" : re.compile("^ALU54B\s+(\d+)"),
"018 ALU24B" : re.compile("^ALU24B\s+(\d+)"),
"019 PRADD18A" : re.compile("^PRADD18A\s+(\d+)"),
"019 PRADD9A" : re.compile("^PRADD9A\s+(\d+)"),
"020 MULT36X36B" : re.compile("^MULT36X36B\s+(\d+)"),
"021 MULT18X18B" : re.compile("^MULT18X18B\s+(\d+)"),
"022 MULT18X18MACB" : re.compile("^MULT18X18MACB\s+(\d+)"),
"023 MULT18X18ADDSUBB" : re.compile("^MULT18X18ADDSUBB\s+(\d+)"),
"024 MULT18X18ADDSUBSUMB" : re.compile("^MULT18X18ADDSUBSUMB\s+(\d+)"),
"025 MULT9X9B" : re.compile("^MULT9X9B\s+(\d+)"),
"026 MULT9X9ADDSUBB" : re.compile("^MULT9X9ADDSUBB\s+(\d+)"),
"027 MULT18X18C" : re.compile("^MULT18X18C\s+(\d+)"),
"028 MULT9X9C" : re.compile("^MULT9X9C\s+(\d+)"),
"029 ALU54A" : re.compile("^ALU54A\s+(\d+)"),
"030 ALU24A" : re.compile("^ALU24A\s+(\d+)"),
"stop" : re.compile("^Page\s+8"),
"100 MapCPUTime" : re.compile("^Total CPU Time:\s+(.+)"),
"101 MapPeakMem" : re.compile("^Peak Memory Usage:\s+(\d+) MB")
# Total CPU Time: 0 secs
# Peak Memory Usage: 51 MB
}
self.patterns_for_clocks={
# Number of clocks: 1
"001 clocks" : re.compile("^Number\s+of\s+clocks:\s+(\d+)"),
#Net mclkin_c: 787 loads, 785 rising, 2 falling (Driver: PIO mclkin )
"002 loads" : re.compile("^Net\s+(.+):\s+(\d+)\s+loads"),
"stop" : re.compile("^Page\s+8")
}
self.reset()
self.data_clocks = {}
def __init__(self):
ScanBasic.__init__(self)
self.reset()
self.title = ["IO", "fmax", "clkName","targetFmax"]
self.data = ['NA']*len(self.title)
def __init__(self):
ScanBasic.__init__(self)
self.patterns = {
"001 edif2ngd": re.compile("^([\.\d]+)\s+,\s+\S+edif2ngd\s+"),
"002 ngdbuild": re.compile("^([\.\d]+)\s+,\s+\S+ngdbuild\s+"),
"003 map": re.compile("^([\.\d]+)\s+,\s+\S+map\s+"),
"004 par": re.compile("^([\.\d]+)\s+,\s+\S+par\s+"),
"005 trce": re.compile("^([\.\d]+)\s+,\s+\S+trce\s+")
}
self.patterns_srr = {
#Process took 0h:00m:01s realtime, 0h:00m:01s cputime
"001 srr_time":
re.compile("^Process\s+took\s+(.+)\s+realtime,\s+(.+)\s+cputime"),
#CCU2D: 88 #synthesis
#CCU2D => 85 #lse
"002 CCU_lse":
re.compile("^CCU.*?\s+(\d+)"),
#Peak Memory Usage: 125.008 MB
"003 SynPeakMem":
re.compile("^Peak\sMemory\sUsage:\s+([\d.]+)"),
#Elapsed CPU time for LSE flow : 7.301 secs
"004 lse_CPU_Time":
re.compile(
"^Elapsed\s+CPU\s+time\s+for\s+LSE\s+flow\s+:\s+([\d.]+)"),
"005 PostLSEClk_PostLSEFmax":
re.compile(
'''create_clock\s+-period\s+\S+\s+-name\s+
\S+\s+
\[get_nets\s+(\S+?)\]\s+
[\.\d]+\s+MHz\s+
([\.\d]+)\s+MHz''', re.VERBOSE | re.I),
#Peak Memory Usage: 51.152 MB
"007 LsePeakMem":
re.compile("^Peak\sMemory\sUsage:\s+([\d.]+)"),
}
self.patterns_mrp = {
# Total CPU Time: 3 secs
"001 mrp_CPU_Time": re.compile("Total\s+CPU\s+Time:\s+(.+)"),
# Total REAL Time: 4 secs
"002 mrp_REAL_Time": re.compile("Total\s+REAL\s+Time:\s+(.+)")
}
self.patterns_par = {
#Total CPU time 1 mins 41 secs
"001 par_CPU_Time":
re.compile("Total\s+CPU\s+time\s+to\s+completion:?\s+(.+)"),
#Total REAL time: 1 mins 42 secs
"002 par_REAL_Time":
re.compile("Total\s+REAL\s+time\s+to\s+completion:\s+(.+)"),
"003 Complete":
re.compile("All signals are completely routed."),
"004 Par_Done":
re.compile("par done!"),
#PAR peak memory usage: 59.777 Mbytes
"005 ParPeakMem":
re.compile("PAR\s+peak\s+memory\s+usage:\s+([\d \.]+)\s+Mbytes")
}
self.srr_data = {
'srr_Real_time': 'NA',
'srr_Cpu_time': 'NA',
'CCU_lse': 'NA',
'SynPeakMem': 'NA',
'lse_CPU_Time': 'NA',
'PostLSEClk': 'NA',
'PostLSEFmax': 'NA',
'LsePeakMem': 'NA'
}
self.mrp_time = {}
for key in self.patterns_mrp.keys():
key = key.split()[1]
self.mrp_time[key] = 'NA'
self.par_data = {}
for key in self.patterns_par.keys():
key = key.split()[1]
self.par_data[key] = 'NA'
self.reset()