import sys
sys.path.append("../software/py")
from trace_gen import TraceGen
from npa_addr_gen import NPAAddrGen
tg = TraceGen(addr_width_p=39, data_width_p=64)
npa = NPAAddrGen(y_cord_width_p=1, x_cord_width_p=2, epa_addr_width_p=10)
tg.print_header()
# wait for CCE to do initialization sequence
tg.wait(5000)
npa_addr = npa.get_npa_addr(y=1,x=0,epa_addr=0)
tg.send_store(size=8, addr=(npa_addr | (1 << 38)), data=1234567890)
tg.recv_data(data=0)
tg.send_load(size=8, addr=(npa_addr | (1 << 38)), signed=0)
tg.recv_data(data=1234567890)
npa_addr = npa.get_npa_addr(y=1,x=0,epa_addr=2)
tg.send_store(size=8, addr=(npa_addr | (1 << 38)), data=0x1133557722446688)
tg.recv_data(data=0)
tg.send_load(size=1, addr=(npa_addr | (1 << 38))+0, signed=0)
tg.recv_data(data=0x88)
tg.send_load(size=1, addr=(npa_addr | (1 << 38))+1, signed=0)
tg.recv_data(data=0x66)
tg.send_load(size=1, addr=(npa_addr | (1 << 38))+2, signed=0)
tg.recv_data(data=0x44)
tg.send_load(size=1, addr=(npa_addr | (1 << 38))+3, signed=0)
tg.recv_data(data=0x22)
class TestGenerator(object):
def __init__(self, paddr_width=40, data_width=64, debug=False):
self.paddr_width = paddr_width
self.data_width = data_width
self.tg = TraceGen(addr_width_p=self.paddr_width,
data_width_p=self.data_width)
self.debug = debug
def eprint(self, *args, **kwargs):
print(*args, file=sys.stderr, **kwargs)
def generateTrace(self, ops):
# preamble
self.tg.print_header()
self.tg.wait(100)
for (st, addr, size, uc, val) in ops:
if st:
self.tg.send_store(size=size, addr=addr, data=val, uc=uc)
self.tg.recv_data(addr=addr, data=0, uc=uc)
else:
# TODO: signed operations
self.tg.send_load(signed=0, size=size, addr=addr, uc=uc)
self.tg.recv_data(addr=addr, data=val, uc=uc)
# test end
self.tg.test_done()
# single cached store
def storeTest(self, mem_base=0):
addr = mem_base
return [(True, addr, 8, 0, 1)]
# cached store/load pair
def loadTest(self, mem_base=0):
addr = mem_base
return [(True, addr, 8, 0, 1), (False, addr, 8, 0, 1)]
# fill a cache set with stores
# evict an entry
# load back the entry
def setTest(self, mem_base=0, assoc=8, sets=64, block_size=64):
ops = []
addr = mem_base
# blocks in same set are separated by (sets*block_size) in byte-addressable memory
stride = sets * block_size
store_val = 1
for i in range(assoc + 1):
ops.append((True, addr, 8, 0, store_val))
addr += stride
store_val += 1
ops.append((False, mem_base, 8, 0, 1))
return ops
# Random loads and stores to a single set (set 0)
def setHammerTest(self,
N=16,
mem_base=0,
mem_bytes=1024,
mem_block_size=64,
mem_size=2,
assoc=8,
sets=64,
seed=0,
lce_mode=0):
# test begin
random.seed(seed)
ops = []
mem = TestMemory(mem_base, mem_bytes, mem_block_size, self.debug)
# compute block addresses for all blocks mapping to set 0
blocks = [i * sets * mem_block_size for i in range(assoc * mem_size)]
store_val = 1
for i in range(N):
# pick access parameters
store = random.choice([True, False])
size = random.choice([1, 2, 4, 8])
size_shift = int(math.log(size, 2))
# determine type of request (cached or uncached)
uncached_req = 0
if lce_mode == 2:
uncached_req = random.choice([0, 1])
elif lce_mode == 1:
uncached_req = 1
# choose which cache block in memory to target
block = random.choice(blocks)
# choose offset in cache block based on size of access ("word" size for this access)
words = mem_block_size / size
word = random.randint(0, words - 1)
# build the address
addr = block + (word << size_shift) + mem_base
mem.check_valid_addr(addr)
val = 0
if store:
# NOTE: the value being stored will be truncated to size number of bytes
store_val_trunc = store_val
if (size < 8):
store_val_trunc = store_val_trunc & ~(~0 << (size * 8))
mem.write_memory(addr, store_val_trunc, size)
val = store_val_trunc
store_val += 1
else:
val = mem.read_memory(addr, size)
ops.append((store, addr, size, uncached_req, val))
return ops
# Random loads and stores to a single cache block
def blockTest(self, N=16, mem_base=0, block_size=64, seed=0):
return self.randomTest(N, mem_base, block_size, block_size, seed, 0)
# Random Test generator
# N is number of operations
# lce_mode = 0, 1, or 2 -> 0 = cached only, 1 = uncached only, 2 = mixed
def randomTest(self,
N=16,
mem_base=0,
mem_bytes=1024,
mem_block_size=64,
seed=0,
lce_mode=0):
# test begin
random.seed(seed)
ops = []
mem = TestMemory(mem_base, mem_bytes, mem_block_size, self.debug)
mem_blocks = mem_bytes / mem_block_size
b = int(math.log(mem_block_size, 2))
store_val = 1
for i in range(N):
# pick access parameters
store = random.choice([True, False])
size = random.choice([1, 2, 4, 8])
size_shift = int(math.log(size, 2))
# determine type of request (cached or uncached)
uncached_req = 0
if lce_mode == 2:
uncached_req = random.choice([0, 1])
elif lce_mode == 1:
uncached_req = 1
# choose which cache block in memory to target
block = random.randint(0, mem_blocks - 1)
# choose offset in cache block based on size of access ("word" size for this access)
words = mem_block_size / size
word = random.randint(0, words - 1)
# build the address
addr = (block << b) + (word << size_shift) + mem_base
mem.check_valid_addr(addr)
val = 0
if store:
# NOTE: the value being stored will be truncated to size number of bytes
store_val_trunc = store_val
if (size < 8):
store_val_trunc = store_val_trunc & ~(~0 << (size * 8))
mem.write_memory(addr, store_val_trunc, size)
val = store_val_trunc
store_val += 1
else:
val = mem.read_memory(addr, size)
ops.append((store, addr, size, uncached_req, val))
# return the test operations
return ops
#
# bsg_trace_rom_2.py
#
# rom for icache1
#
import sys
sys.path.append("../py/")
from trace_gen import TraceGen
tg = TraceGen(addr_width_p=22, data_width_p=64)
# preamble
tg.print_header()
# test begin
addr_offset = (1<<12)
tg.wait(25000)
for i in range(16):
load_data = (i+1)*(i+1)
tg.send_load(signed=0, size=4, addr=addr_offset+(i*8))
tg.recv_data(data=load_data)
tg.send_load(signed=0, size=4, addr=addr_offset+(i*8)+4)
tg.recv_data(data=load_data)
# test end
tg.test_done()
#eprint('write: mem[{0}] := {1:x}'.format(addr+i, v))
mem[addr + i] = v
#write_memory(byte_memory, 0, 256, 2)
#print(read_memory(byte_memory, 0, 1))
tg = TraceGen(addr_width_p=args.paddr_width, data_width_p=args.dword_size)
# preamble
tg.print_header()
# test begin
random.seed(args.seed)
tg.wait(100)
store_val = 1
for i in range(args.num_instr):
# pick access parameters
load = random.choice([True, False])
size = random.choice([1, 2, 4, 8])
size_shift = int(math.log(size, 2))
# choose which cache block in memory to target
block = random.randint(0, mem_blocks - 1)
#eprint('block: {0}'.format(block))
# choose offset in cache block based on size of access ("word" size for this access)
words = cache_block_size_bytes / size
word = random.randint(0, words - 1)
#eprint('word: {0}'.format(word))
from trace_gen import TraceGen WAIT_TIME = 50 ways = 8 sets = 16 block_size_bytes = 64 cache_size = block_size_bytes * ways * sets size = 1 addr_inc = block_size_bytes * sets tg = TraceGen(addr_width_p=20, data_width_p=64) # preamble tg.print_header() # test begin addr = 0 data = 0 tg.wait(WAIT_TIME*100) for i in xrange(0,ways): tg.send_load(signed=0, size=size, addr=addr) tg.recv_data(data=data) addr = addr + addr_inc data = data + 1 # test end tg.test_done()
class TestGenerator(object):
def __init__(self, paddr_width=40, data_width=64, debug=False):
self.paddr_width = paddr_width
self.data_width = data_width
self.tg = TraceGen(addr_width_p=self.paddr_width,
data_width_p=self.data_width)
self.debug = debug
def eprint(self, *args, **kwargs):
print(*args, file=sys.stderr, **kwargs)
# Write ops to file
# ops is a dictionary, indexed by thread ID (integer) as key
# the values are lists of command tuples
def generateTrace(self, ops, out_dir, out_file_base):
for lce in ops:
file_name = '{0}_{1}.tr'.format(out_file_base, lce)
with open(os.path.join(out_dir, file_name), 'w') as lce_trace_file:
# preamble
lce_trace_file.write(self.tg.print_header())
lce_trace_file.write(self.tg.wait(100))
# commands
for (cmd, addr, size, uc, val) in ops[lce]:
if cmd == 'store':
lce_trace_file.write(
self.tg.send_store(size=size,
addr=addr,
data=val,
uc=uc))
lce_trace_file.write(
self.tg.recv_store(size=size, addr=addr, uc=uc))
elif cmd == 'load':
lce_trace_file.write(
self.tg.send_load(signed=0,
size=size,
addr=addr,
uc=uc))
lce_trace_file.write(
self.tg.recv_load(signed=0,
size=size,
addr=addr,
data=val,
uc=uc))
elif cmd == 'wait':
# addr is used as number of cycles
lce_trace_file.write(self.tg.wait(addr))
# test end
lce_trace_file.write(self.tg.test_done())
# read trace from file
def readTrace(self, infile):
ops = {}
with open(infile, 'r') as trace_file:
for raw_line in trace_file:
trim_line = raw_line.strip()
if not trim_line.startswith('#') and trim_line:
# cmd = thread: load/store addr size uc value
# cmd = thread: wait cycles
line = [x.strip() for x in trim_line.split(':')]
thread = int(line[0])
cmd = [x.strip() for x in line[1].split(' ')]
if not thread in ops:
ops[thread] = []
if cmd[0] == 'wait':
cycles = int(cmd[1])
ops[thread].append(('wait', cycles, 0, 0, 0))
else:
op = cmd[0]
if not (op == 'store' or op == 'load'):
self.eprint(
'[ME TraceGen]: unrecognized op in trace file: {0}'
.format(op))
return {}
addr = int(cmd[1], 16)
size = int(cmd[2])
uc = int(cmd[3])
if (cmd[4].startswith('0x')):
value = int(cmd[4], 16)
else:
value = int(cmd[4])
ops[thread].append((op, addr, size, uc, value))
return ops
# Random Test generator
# N is number of operations
# lce_mode = 0, 1, or 2 -> 0 = cached only, 1 = uncached only, 2 = mixed
# cache_sets is number of sets in the cache
# lce is number of LCEs to use (multi-LCE requires axe=True)
# test_sets is number of cache sets to use in test
# test_ways is number of cache ways per set to use in test
def randomTest(self,
N=16,
mem_base=0,
cache_sets=64,
block_size=64,
seed=0,
lce_mode=0,
lce=1,
test_sets=64,
test_ways=2,
axe=False):
random.seed(seed)
ops = {i: [] for i in range(lce)}
# test memory - large enough for full number of cache sets across test_ways number of ways
mem_blocks = (cache_sets * test_ways)
mem_bytes = (mem_blocks * block_size)
mem = TestMemory(mem_base, mem_bytes, block_size, self.debug)
# generate collection of block IDs that are used for testing
# start with set 0 and use test_sets number of sets across test_ways number of ways
test_blocks = [
s + w * cache_sets for s in range(test_sets)
for w in range(test_ways)
]
b = int(math.log(block_size, 2))
store_val = 1
for i in range(N):
for l in range(lce):
# pick access parameters
store = random.choice([True, False])
# all accesses are size 8B for AXE tracing
size = 8 if axe else random.choice([1, 2, 4, 8])
size_shift = int(math.log(size, 2))
# determine type of request (cached or uncached)
uncached_req = 0
if lce_mode == 2:
uncached_req = random.choice([0, 1])
elif lce_mode == 1:
uncached_req = 1
# choose which cache block to access
block = random.choice(test_blocks)
# choose offset in cache block based on size of access ("word" size for this access)
words = block_size / size
word = random.randint(0, words - 1)
# build the address
addr = (block << b) + (word << size_shift) + mem_base
mem.check_valid_addr(addr)
val = 0
if store:
# note: the value being stored will be truncated to size number of bytes
store_val_trunc = store_val
if (size < 8):
store_val_trunc = store_val_trunc & ~(~0 << (size * 8))
if not axe:
mem.write_memory(addr, store_val_trunc, size)
val = store_val_trunc
store_val += 1
elif not axe:
val = mem.read_memory(addr, size)
ops[l].append(('store' if store else 'load', addr, size,
uncached_req, val))
# return the test operations
return ops
def main():
tracer = TraceGen(28, 12, 4, 64)
# Store/Load double word test
file = open("test_sd_ld.tr", "w")
file.write(tracer.print_header())
file.write(tracer.print_comment("Wait for SYNC"))
file.write(tracer.wait(65))
file.write(tracer.print_comment("Store to address - 0, 8, 16, 24, 32, 40, 48, 56"))
for i in range(8, 72, 8):
file.write(tracer.send_store(8, i-8, 0, False, i))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Load from address - 0, 8, 16, 24, 32, 40, 48, 56"))
for i in range(8, 72, 8):
file.write(tracer.send_load(True, 8, i-8, 0, False))
file.write(tracer.recv_data(i))
file.write(tracer.print_comment("Store/Load double word test done\n"))
file.write(tracer.test_finish())
file.close()
# Store/Load byte test (signed and unsigned)
file = open("test_sb_lb.tr", "w")
file.write(tracer.print_header())
file.write(tracer.print_comment("Wait for SYNC"))
file.write(tracer.wait(65))
file.write(tracer.print_comment("Store byte to address 64"))
file.write(tracer.send_store(1, 64, 0, False, 170))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Load signed byte from address 64"))
file.write(tracer.send_load(True, 1, 64, 0, False))
file.write(tracer.recv_data(-86))
file.write(tracer.print_comment("Load unsigned byte from address 64"))
file.write(tracer.send_load(False, 1, 64, 0, False))
file.write(tracer.recv_data(170))
file.write(tracer.print_comment("Store/Load unsigned/signed byte test done\n"))
file.write(tracer.test_finish())
file.close()
# Store/Load halfword test (signed and unsigned)
file = open("test_sh_lh.tr", "w")
file.write(tracer.print_header())
file.write(tracer.print_comment("Store halfword to address 128"))
file.write(tracer.print_comment("Wait for SYNC"))
file.write(tracer.wait(65))
file.write(tracer.send_store(2, 128, 0, False, 43690))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Load signed halfword from address 128"))
file.write(tracer.send_load(True, 2, 128, 0, False))
file.write(tracer.recv_data(-21846))
file.write(tracer.print_comment("Load unsigned halfword from address 128"))
file.write(tracer.send_load(False, 2, 128, 0, False))
file.write(tracer.recv_data(43690))
file.write(tracer.print_comment("Store/Load unsigned/signed halfword test done\n"))
file.write(tracer.test_finish())
file.close()
# Store/Load word test (signed and unsigned)
file = open("test_sw_lw.tr", "w")
file.write(tracer.print_header())
file.write(tracer.print_comment("Wait for SYNC"))
file.write(tracer.wait(65))
file.write(tracer.print_comment("Store word to address 192"))
file.write(tracer.send_store(4, 192, 0, False, 2863311530))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Load signed word from address 192"))
file.write(tracer.send_load(True, 4, 192, 0, False))
file.write(tracer.recv_data(-1431655766))
file.write(tracer.print_comment("Load unsigned word from address 192"))
file.write(tracer.send_load(False, 4, 192, 0, False))
file.write(tracer.recv_data(2863311530))
file.write(tracer.print_comment("Store/Load unsigned/signed word test done\n"))
file.write(tracer.test_finish())
file.close()
# Store to same index with 9 different ptags (to verify writeback)
file = open("test_wb.tr", "w")
file.write(tracer.print_header())
file.write(tracer.print_comment("Wait for SYNC"))
file.write(tracer.wait(65))
file.write(tracer.print_comment("Store to address - 256, 4352, 8448, 12544, 16640, 20736, 24832, 28928"))
for i in range(8, 72, 8):
temp_ptag = ((i-1) >> 3)
file.write(tracer.send_store(8, 256, temp_ptag, False, i))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Load from the above addresses to verify store."))
for i in range(8, 72, 8):
temp_ptag = (i-1) >> 3
file.write(tracer.send_load(True, 8, 256, temp_ptag, False))
file.write(tracer.recv_data(i))
file.write(tracer.print_comment("Store to same cache index but different physical address - address 33024"))
file.write(tracer.send_store(8, 256, 8, False, 72))
file.write(tracer.print_comment("Receive zero (to dequeue fifo)"))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Load from address 33024"))
file.write(tracer.send_load(True, 8, 256, 8, False))
file.write(tracer.recv_data(72))
file.write(tracer.print_comment("Load from address - 256"))
file.write(tracer.send_load(True, 8, 256, 0, False))
file.write(tracer.recv_data(8))
file.write(tracer.print_comment("Load from address 33024"))
file.write(tracer.send_load(True, 8, 256, 8, False))
file.write(tracer.recv_data(72))
file.write(tracer.print_comment("Writeback, Eviction and Replacement successfully tested"))
file.write(tracer.test_finish())
file.close()
# Uncached Store/Load
file = open("test_uncached.tr", "w")
file.write(tracer.print_header())
file.write(tracer.print_comment("Wait for SYNC"))
file.write(tracer.wait(65))
file.write(tracer.print_comment("Store to address 320 in uncached mode"))
file.write(tracer.send_store(8, 320, 0, True, 320))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Load from address 320 in uncached mode"))
file.write(tracer.send_load(True, 8, 320, 0, True))
file.write(tracer.recv_data(320))
file.write(tracer.test_finish())
file.close()
# Unaligned accesses
file = open("test_unaligned.tr", "w")
file.write(tracer.print_header())
file.write(tracer.print_comment("Wait for SYNC"))
file.write(tracer.wait(65))
file.write(tracer.print_comment("Store byte to address - 7"))
file.write(tracer.send_store(1, 7, 0, False, 255))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Store halfword to address - 2"))
file.write(tracer.send_store(2, 2, 0, False, 1010))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Load byte from address - 7"))
file.write(tracer.send_load(False, 1, 7, 0, False))
file.write(tracer.recv_data(255))
file.write(tracer.print_comment("Load halfword from address - 2"))
file.write(tracer.send_load(False, 2, 2, 0, False))
file.write(tracer.recv_data(1010))
file.write(tracer.print_comment("Store word to address - 4"))
file.write(tracer.send_store(4, 4, 0, False, 70000))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Load word from address - 4"))
file.write(tracer.send_load(False, 4, 4, 0, False))
file.write(tracer.recv_data(70000))
file.write(tracer.print_comment("Store \"byte\" to address - 1"))
file.write(tracer.send_store(1, 1, 0, False, 256))
file.write(tracer.recv_data(0))
file.write(tracer.print_comment("Load byte from address - 1"))
file.write(tracer.send_load(False, 1, 1, 0, False))
file.write(tracer.recv_data(0))
file.write(tracer.test_finish())
file.close()
#
# bsg_trace_rom_3.py
#
# rom for dcache1
#
import sys
sys.path.append("../py/")
from trace_gen import TraceGen
tg = TraceGen(addr_width_p=22, data_width_p=64)
# preamble
tg.print_header()
# test begin
addr_offset = (1 << 12)
tg.wait(20000)
for i in range(16):
store_data = ((i + 1) * (i + 1) << 32) + (i + 1) * (i + 1)
tg.send_store(size=8, addr=addr_offset + (i * 8), data=store_data)
tg.recv_data(data=0)
# test end
tg.test_done()
#
# bsg_trace_rom_1.py
#
# rom for dcache0
#
import sys
sys.path.append("../py/")
from trace_gen import TraceGen
tg = TraceGen(addr_width_p=22, data_width_p=64)
# preamble
tg.print_header()
# test begin
tg.send_store(size=8, addr=0, data=1)
tg.recv_data(data=0)
tg.wait(60)
tg.send_store(size=8, addr=0, data=2)
tg.recv_data(data=0)
tg.wait(60)
tg.send_load(size=8, addr=0, signed=0)
tg.recv_data(data=2)
# test end
tg.test_done()
import sys
sys.path.append("../py/")
from trace_gen import TraceGen
tg = TraceGen(addr_width_p=22, data_width_p=64)
# preamble
tg.print_header()
# test begin
tg.wait(16)
tg.send_load(signed=0, size=8, addr=0)
tg.recv_data(data=1)
# test end
tg.test_done()
# bsg_trace_rom_0.py
#
# rom for icache0
#
import sys
sys.path.append("../py/")
from trace_gen import TraceGen
tg = TraceGen(addr_width_p=22, data_width_p=64)
# preamble
tg.print_header()
# test begin
tg.wait(8)
tg.send_load(signed=0, size=4, addr=0)
tg.send_load(signed=0, size=4, addr=4)
tg.recv_data(data=1)
tg.recv_data(data=0)
tg.wait(100)
tg.send_load(signed=0, size=4, addr=0)
tg.send_load(signed=0, size=4, addr=4)
tg.recv_data(data=2)
tg.recv_data(data=0)
tg.wait(150)
tg.send_load(signed=0, size=4, addr=0)
tg.send_load(signed=0, size=4, addr=4)
tg.recv_data(data=2)
