#
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
# KIND, either express or implied. See the License for the
# specific language governing permissions and limitations
# under the License.
import tvm
import numpy as np
import tsim
def test_accel():
rmax = 64
dtype = "uint64"
n = 1 << np.random.randint(0, 5)
ctx = tvm.cpu(0)
a = tvm.nd.array(np.random.randint(rmax, size=n).astype(dtype), ctx)
b = tvm.nd.array(np.random.randint(rmax, size=n).astype(dtype), ctx)
c = tvm.nd.array(np.zeros(n).astype(dtype), ctx)
f = tsim.load_module()
f(a, b, c)
msg = "n:{}".format(n)
np.testing.assert_equal(c.asnumpy(), a.asnumpy() + b.asnumpy(), err_msg = "[FAIL] " + msg)
print("[PASS] " + msg)
if __name__ == "__main__":
tsim.init()
for i in range(8):
test_accel()
else:
cycles += f(a_arr[i], b_arr[j], shift, accum,
np.uint32(0)) # no reset
return (accum.asnumpy()[0], cycles)
def top_test(dtype, w_width, a_width):
rmax = np.random.randint(256)
# prevent generating empty matrix
rrow = np.random.randint(31) + 1
rclmn = 8
rrow2 = np.random.randint(31) + 1
A = np.random.randint(rmax, size=(rrow, rclmn)).astype(dtype)
B = np.random.randint(rmax, size=(rclmn, rrow2)).astype(dtype)
print("A: ")
print(A)
print("\n")
print("B: ")
print(B)
print("\n")
matrix_multiply(A, B, w_width, a_width)
if __name__ == "__main__":
tsim.init("chisel")
for i in range(1):
top_test("uint8", 8, 8)
# Unless required by applicable law or agreed to in writing,
# software distributed under the License is distributed on an
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
# KIND, either express or implied. See the License for the
# specific language governing permissions and limitations
# under the License.
import tvm
from tvm import te
import numpy as np
import tsim
def test_accel():
rmax = 64
dtype = "uint64"
n = np.random.randint(1, rmax)
c = np.random.randint(0, rmax)
ctx = tvm.cpu(0)
a = tvm.nd.array(np.random.randint(rmax, size=n).astype(dtype), ctx)
b = tvm.nd.array(np.zeros(n).astype(dtype), ctx)
f = tsim.load_module()
cycles = f(a, b, c)
msg = "cycles:{0:4} n:{1:2} c:{2:2}".format(cycles, n, c)
np.testing.assert_equal(b.asnumpy(), a.asnumpy() + c, err_msg = "[FAIL] " + msg)
print("[PASS] " + msg)
if __name__ == "__main__":
tsim.init("verilog")
for i in range(10):
test_accel()
