def getIOstates(self):
'''
return a tuple of 3 booleans for each channel, which represent:
- type: analog (in) (True) or digital (False)
- digital direction: output (True) or input (False)
- digital state: high (True) or low (False)
'''
adprops = self.configIO()
dirs = self._feedback_command(u3.PortDirRead())
states = self._feedback_command(u3.PortStateRead())
channelSettings = []
fiotypes = self.int_to_bitarray(adprops['FIOAnalog'])
fiodirs = self.int_to_bitarray(dirs['FIO'])
fiostates = self.int_to_bitarray(states['FIO'])
for tup in zip(fiotypes, fiodirs, fiostates):
channelSettings.append(tup)
eiotypes = self.int_to_bitarray(adprops['EIOAnalog'])
eiodirs = self.int_to_bitarray(dirs['EIO'])
eiostates = self.int_to_bitarray(states['EIO'])
for tup in zip(eiotypes, eiodirs, eiostates):
channelSettings.append(tup)
ciotypes = 4 * [False] # these cannot be analog
ciodirs = self.int_to_bitarray(dirs['CIO'], bits=4)
ciostates = self.int_to_bitarray(states['CIO'], bits=4)
for tup in zip(ciotypes, ciodirs, ciostates):
channelSettings.append(tup)
return channelSettings
def read(self):
"""
read the bit pattern at a latch
The state of NLOAD is normallly high. When checking status (or reading
bits), toggle NLOAD low for at least 10 mS then high to store the
information for reading.
CS-BUS is the global enable. The normal state is high. Set to this to low
when programming latches or reading data. Then set high when done.
@return: byte
"""
self.logger.debug(" read: Reading latch %d", self.address)
# Select the latch to be read
if self.setLatchAddr(read=True):
port_states = self.LJ.getFeedback(u3.PortStateRead())
self.logger.debug(" read: port states to check latch address: %s", port_states)
latchAddr = port_states[0]['EIO']
#self.logger.debug(" read: LatchGroup address is %d",latchAddr)
if latchAddr != self.address and latchAddr != (self.address | 4):
self.logger.debug(" read: Requested latch %d but got %d",
self.address, latchAddr)
return None
else:
#self.logger.debug(" read: latch address set to %d", self.address)
portStates = self.set_signals(
{"SCK":1, "SDI":1,"NLOAD":1, "CS-BUS":1})
# Store the information to be read from this address
self.set_signals({"NLOAD":0})
self.set_signals({"NLOAD":1})
# Enable serial data transfer
self.set_signals({"CS-BUS":0})
MBDATA = 0
# Process from MS to LS bit
for bit in range(7,-1,-1):
try:
state = self.LJ.getFeedback(
u3.BitStateRead(IONumber = WBDCsignal["SDO"]))[0]
#self.logger.debug(" read: bit %d state is %d for MBDATA = %d",
# bit, state, MBDATA)
except Exception as details:
self.logger.error(" read: Data In failed at bit %d\n%s",
bit, details)
return None
if state:
MBDATA = Math.Bin.setbit(MBDATA, bit)
if bit > 0:
self.set_signals({"SCK":0})
self.set_signals({"SCK":1})
self.set_signals({"CS-BUS":1})
return MBDATA
else:
self.logger.error(" read: Setting latch address failed")
return -1
def set_signals(self, signal_dict):
"""
Sets signals for programming and reading data.
The signals are provided as a dictionary with the keys as signal names
defined in WBDCsignal. For example:
>>> set_signals(LJ,{"SCK":1, "SDA":1,"NLOAD":1, "CS-BUS":1})
Invoked with an empty dictionary it returns the state of the digital
I/O ports:
In [3]: set_signals(lj[1],{})
Out[3]: [{'CIO': 15, 'EIO': 86, 'FIO': 240}]
To give the signals time to settle, a 10 ms wait is included. Until
Python 2.6, time.sleep() must be used.
@type signal_dict : dictionary
@param signal_dict : signal names and states
@return: result of u3.BitStateWrite()
"""
commands = []
for signal,state in list(signal_dict.items()):
commands.append(u3.BitStateWrite(WBDCsignal[signal], state))
commands.append(u3.PortStateRead())
#self.logger.debug(" set_signals: sending %s", commands)
try:
result = self.LJ.getFeedback(commands)
#self.logger.debug(" set_signals: command feedback: %s", result)
#if float(python_version()[:3]) < 2.6:
time.sleep(0.01)
except Exception as details:
self.logger.error(" set_signals: LJ commands failed:\n%s", details)
return result[-1]
try:
#Configure the IOs before the test starts
FIOEIOAnalog = (2**numChannels) - 1
fios = FIOEIOAnalog & (0xFF)
eios = FIOEIOAnalog / 256
d.configIO(FIOAnalog=fios, EIOAnalog=eios)
d.getFeedback(u3.PortDirWrite(Direction=[0, 0, 0], WriteMask=[0, 0, 15]))
feedbackArguments = []
feedbackArguments.append(u3.DAC0_8(Value=125))
feedbackArguments.append(u3.PortStateRead())
#Check if the U3 is an HV
if d.configU3()['VersionInfo'] & 18 == 18:
isHV = True
else:
isHV = False
for i in range(numChannels):
feedbackArguments.append(
u3.AIN(i, 31, QuickSample=quickSample, LongSettling=longSettling))
#print feedbackArguments
start = datetime.now()
# Call Feedback 1000 times
def __readAllDIO(self):
return self.u.getFeedback(u3.PortStateRead())
def read(self, state): self.labjack.getFeedback(u3.PortStateRead([state, 0, 0]))
EAINvalues[AIN][0], isLowVoltage=True, isSingleEnded=True)
FAINvalues = self.get_AINs("F")
for AIN in FAINvalues.keys():
response[AIN] = self.binaryToCalibratedAnalogVoltage(
FAINvalues[AIN][0], isLowVoltage=True, isSingleEnded=True)
try:
bitdirs = self.getFeedback(u3.PortDirRead())[0]
except Exception, details:
self.logger.error("Could not get direction bits for LabJack %d",
self.localID)
else:
response["CIOBitDir"] = bitdirs["CIO"]
response["EIOBitDir"] = bitdirs["EIO"]
response["FIOBitDir"] = bitdirs["FIO"]
try:
bitstates = self.getFeedback(u3.PortStateRead())[0]
except Exception, details:
self.logger.error("Could not get states of bits for LabJack %s",
self.localID)
else:
response["CIOState"] = bitstates["CIO"]
response["EIOState"] = bitstates["EIO"]
response["FIOState"] = bitstates["FIO"]
response["Temperature"] = self.getTemperature()
self.IO_state = response
return self.IO_state
class LJTickDAC(MCobject):
"""
Each FIO section, when configured for digital output, can accomodate a
