def bench(): # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) output_axis_tready = Signal(bool(0)) rxd = Signal(bool(1)) prescale = Signal(intbv(0)[16:]) # Outputs output_axis_tdata = Signal(intbv(0)[8:]) output_axis_tvalid = Signal(bool(0)) busy = Signal(bool(0)) overrun_error = Signal(bool(0)) frame_error = Signal(bool(0)) # sources and sinks sink_pause = Signal(bool(0)) source = uart_ep.UARTSource() source_logic = source.create_logic(clk, rst, txd=rxd, prescale=prescale, name='source') sink = axis_ep.AXIStreamSink() sink_logic = sink.create_logic(clk, rst, tdata=output_axis_tdata, tvalid=output_axis_tvalid, tready=output_axis_tready, pause=sink_pause, name='sink') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, output_axis_tdata=output_axis_tdata, output_axis_tvalid=output_axis_tvalid, output_axis_tready=output_axis_tready, rxd=rxd, busy=busy, overrun_error=overrun_error, frame_error=frame_error, prescale=prescale) @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge yield clk.posedge yield clk.posedge prescale.next = 1 yield clk.posedge yield clk.posedge print("test 1: walk") current_test.next = 1 source.write(b'\x00\x01\x02\x04\x08\x10\x20\x40\x80') yield clk.posedge yield delay(5000) yield delay(1000) yield clk.posedge rx_data = bytearray(sink.read()) print(rx_data) assert rx_data == b'\x00\x01\x02\x04\x08\x10\x20\x40\x80' yield clk.posedge print("test 2: walk 2") current_test.next = 2 source.write(b'\x00\x01\x03\x07\x0F\x1F\x3F\x7F\xFF') yield clk.posedge yield delay(5000) yield delay(1000) yield clk.posedge rx_data = bytearray(sink.read()) print(rx_data) assert rx_data == b'\x00\x01\x03\x07\x0F\x1F\x3F\x7F\xFF' yield delay(100) raise StopSimulation return dut, source_logic, sink_logic, clkgen, check
def bench(): # Parameters TARGET = "SIM" # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) btnu = Signal(bool(0)) btnl = Signal(bool(0)) btnd = Signal(bool(0)) btnr = Signal(bool(0)) btnc = Signal(bool(0)) sw = Signal(intbv(0)[4:]) i2c_scl_i = Signal(bool(1)) i2c_sda_i = Signal(bool(1)) phy_gmii_clk = Signal(bool(0)) phy_gmii_rst = Signal(bool(0)) phy_gmii_clk_en = Signal(bool(0)) phy_gmii_rxd = Signal(intbv(0)[8:]) phy_gmii_rx_dv = Signal(bool(0)) phy_gmii_rx_er = Signal(bool(0)) phy_int_n = Signal(bool(1)) uart_rxd = Signal(bool(1)) uart_cts = Signal(bool(1)) s1_scl_i = Signal(bool(1)) s1_sda_i = Signal(bool(1)) s2_scl_i = Signal(bool(1)) s2_sda_i = Signal(bool(1)) # Outputs led = Signal(intbv(0)[8:]) i2c_scl_o = Signal(bool(1)) i2c_scl_t = Signal(bool(1)) i2c_sda_o = Signal(bool(1)) i2c_sda_t = Signal(bool(1)) phy_gmii_txd = Signal(intbv(0)[8:]) phy_gmii_tx_en = Signal(bool(0)) phy_gmii_tx_er = Signal(bool(0)) phy_reset_n = Signal(bool(0)) uart_txd = Signal(bool(1)) uart_rts = Signal(bool(1)) s1_scl_o = Signal(bool(1)) s1_scl_t = Signal(bool(1)) s1_sda_o = Signal(bool(1)) s1_sda_t = Signal(bool(1)) s2_scl_o = Signal(bool(1)) s2_scl_t = Signal(bool(1)) s2_sda_o = Signal(bool(1)) s2_sda_t = Signal(bool(1)) # sources and sinks gmii_source = gmii_ep.GMIISource() gmii_source_logic = gmii_source.create_logic(phy_gmii_clk, phy_gmii_rst, txd=phy_gmii_rxd, tx_en=phy_gmii_rx_dv, tx_er=phy_gmii_rx_er, clk_enable=phy_gmii_clk_en, name='gmii_source') gmii_sink = gmii_ep.GMIISink() gmii_sink_logic = gmii_sink.create_logic(phy_gmii_clk, phy_gmii_rst, rxd=phy_gmii_txd, rx_dv=phy_gmii_tx_en, rx_er=phy_gmii_tx_er, clk_enable=phy_gmii_clk_en, name='gmii_sink') uart_source = uart_ep.UARTSource() uart_source_logic = uart_source.create_logic(clk, rst, txd=uart_rxd, prescale=int(125000000 / (115200 * 8)), name='uart_source') uart_sink = uart_ep.UARTSink() uart_sink_logic = uart_sink.create_logic(clk, rst, rxd=uart_txd, prescale=int(125000000 / (115200 * 8)), name='uart_sink') # I2C memory model 1 i2c_mem1 = i2c.I2CMem(1024) i2c_mem_logic1 = i2c_mem1.create_logic(scl_i=s1_scl_i, scl_o=s1_scl_o, scl_t=s1_scl_t, sda_i=s1_sda_i, sda_o=s1_sda_o, sda_t=s1_sda_t, abw=2, address=0x50, latency=0, name='slave1') # I2C memory model 2 i2c_mem2 = i2c.I2CMem(1024) i2c_mem_logic2 = i2c_mem2.create_logic(scl_i=s2_scl_i, scl_o=s2_scl_o, scl_t=s2_scl_t, sda_i=s2_sda_i, sda_o=s2_sda_o, sda_t=s2_sda_t, abw=2, address=0x51, latency=1000, name='slave2') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, btnu=btnu, btnl=btnl, btnd=btnd, btnr=btnr, btnc=btnc, sw=sw, led=led, i2c_scl_i=i2c_scl_i, i2c_scl_o=i2c_scl_o, i2c_scl_t=i2c_scl_t, i2c_sda_i=i2c_sda_i, i2c_sda_o=i2c_sda_o, i2c_sda_t=i2c_sda_t, phy_gmii_clk=phy_gmii_clk, phy_gmii_rst=phy_gmii_rst, phy_gmii_clk_en=phy_gmii_clk_en, phy_gmii_rxd=phy_gmii_rxd, phy_gmii_rx_dv=phy_gmii_rx_dv, phy_gmii_rx_er=phy_gmii_rx_er, phy_gmii_txd=phy_gmii_txd, phy_gmii_tx_en=phy_gmii_tx_en, phy_gmii_tx_er=phy_gmii_tx_er, phy_reset_n=phy_reset_n, phy_int_n=phy_int_n, uart_rxd=uart_rxd, uart_txd=uart_txd, uart_rts=uart_rts, uart_cts=uart_cts) @always_comb def bus(): # emulate I2C wired AND i2c_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o i2c_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o s1_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o s1_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o s2_scl_i.next = i2c_scl_o & s1_scl_o & s2_scl_o s2_sda_i.next = i2c_sda_o & s1_sda_o & s2_sda_o @always(delay(4)) def clkgen(): clk.next = not clk phy_gmii_clk.next = not phy_gmii_clk clk_enable_rate = Signal(int(0)) clk_enable_div = Signal(int(0)) @always(clk.posedge) def clk_enable_gen(): if clk_enable_div.next > 0: phy_gmii_clk_en.next = 0 clk_enable_div.next = clk_enable_div - 1 else: phy_gmii_clk_en.next = 1 clk_enable_div.next = clk_enable_rate - 1 @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 phy_gmii_rst.next = 1 yield clk.posedge rst.next = 0 phy_gmii_rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: enumerate via UDP") current_test.next = 1 pkt = xfcp.XFCPFrame() pkt.path = [] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' test_frame = udp_ep.UDPFrame() test_frame.eth_dest_mac = 0x020000000000 test_frame.eth_src_mac = 0xDAD1D2D3D4D5 test_frame.eth_type = 0x0800 test_frame.ip_version = 4 test_frame.ip_ihl = 5 test_frame.ip_dscp = 0 test_frame.ip_ecn = 0 test_frame.ip_length = None test_frame.ip_identification = 0 test_frame.ip_flags = 2 test_frame.ip_fragment_offset = 0 test_frame.ip_ttl = 64 test_frame.ip_protocol = 0x11 test_frame.ip_header_checksum = None test_frame.ip_source_ip = 0xc0a80181 test_frame.ip_dest_ip = 0xc0a80180 test_frame.udp_source_port = 1234 test_frame.udp_dest_port = 14000 test_frame.payload = pkt.build_axis() test_frame.build() gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame.build_eth().build_axis_fcs().data) # wait for ARP request packet rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = gmii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = arp_ep.ARPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF assert check_frame.eth_src_mac == 0x020000000000 assert check_frame.eth_type == 0x0806 assert check_frame.arp_htype == 0x0001 assert check_frame.arp_ptype == 0x0800 assert check_frame.arp_hlen == 6 assert check_frame.arp_plen == 4 assert check_frame.arp_oper == 1 assert check_frame.arp_sha == 0x020000000000 assert check_frame.arp_spa == 0xc0a80180 assert check_frame.arp_tha == 0x000000000000 assert check_frame.arp_tpa == 0xc0a80181 # generate response arp_frame = arp_ep.ARPFrame() arp_frame.eth_dest_mac = 0x020000000000 arp_frame.eth_src_mac = 0xDAD1D2D3D4D5 arp_frame.eth_type = 0x0806 arp_frame.arp_htype = 0x0001 arp_frame.arp_ptype = 0x0800 arp_frame.arp_hlen = 6 arp_frame.arp_plen = 4 arp_frame.arp_oper = 2 arp_frame.arp_sha = 0xDAD1D2D3D4D5 arp_frame.arp_spa = 0xc0a80181 arp_frame.arp_tha = 0x020000000000 arp_frame.arp_tpa = 0xc0a80180 gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + arp_frame.build_eth().build_axis_fcs().data) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = gmii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5 assert check_frame.eth_src_mac == 0x020000000000 assert check_frame.eth_type == 0x0800 assert check_frame.ip_version == 4 assert check_frame.ip_ihl == 5 assert check_frame.ip_dscp == 0 assert check_frame.ip_ecn == 0 assert check_frame.ip_identification == 0 assert check_frame.ip_flags == 2 assert check_frame.ip_fragment_offset == 0 assert check_frame.ip_ttl == 64 assert check_frame.ip_protocol == 0x11 assert check_frame.ip_source_ip == 0xc0a80180 assert check_frame.ip_dest_ip == 0xc0a80181 assert check_frame.udp_source_port == 14000 assert check_frame.udp_dest_port == 1234 rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 64 pkt = xfcp.XFCPFrame() pkt.path = [0] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' test_frame = udp_ep.UDPFrame() test_frame.eth_dest_mac = 0x020000000000 test_frame.eth_src_mac = 0xDAD1D2D3D4D5 test_frame.eth_type = 0x0800 test_frame.ip_version = 4 test_frame.ip_ihl = 5 test_frame.ip_dscp = 0 test_frame.ip_ecn = 0 test_frame.ip_length = None test_frame.ip_identification = 0 test_frame.ip_flags = 2 test_frame.ip_fragment_offset = 0 test_frame.ip_ttl = 64 test_frame.ip_protocol = 0x11 test_frame.ip_header_checksum = None test_frame.ip_source_ip = 0xc0a80181 test_frame.ip_dest_ip = 0xc0a80180 test_frame.udp_source_port = 1234 test_frame.udp_dest_port = 14000 test_frame.payload = pkt.build_axis() test_frame.build() gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame.build_eth().build_axis_fcs().data) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = gmii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5 assert check_frame.eth_src_mac == 0x020000000000 assert check_frame.eth_type == 0x0800 assert check_frame.ip_version == 4 assert check_frame.ip_ihl == 5 assert check_frame.ip_dscp == 0 assert check_frame.ip_ecn == 0 assert check_frame.ip_identification == 0 assert check_frame.ip_flags == 2 assert check_frame.ip_fragment_offset == 0 assert check_frame.ip_ttl == 64 assert check_frame.ip_protocol == 0x11 assert check_frame.ip_source_ip == 0xc0a80180 assert check_frame.ip_dest_ip == 0xc0a80181 assert check_frame.udp_source_port == 14000 assert check_frame.udp_dest_port == 1234 rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [0] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 32 assert gmii_source.empty() assert gmii_sink.empty() yield delay(100) yield clk.posedge print("test 1: test write and read RAM 0") current_test.next = 1 pkt1 = xfcp.XFCPFrame() pkt1.path = [0] pkt1.ptype = 0x12 pkt1.payload = bytearray( struct.pack('<BH', 0, 4) + b'\x11\x22\x33\x44') pkt2 = xfcp.XFCPFrame() pkt2.path = [0] pkt2.ptype = 0x10 pkt2.payload = bytearray(struct.pack('<BH', 0, 4)) test_frame1 = udp_ep.UDPFrame() test_frame1.eth_dest_mac = 0x020000000000 test_frame1.eth_src_mac = 0xDAD1D2D3D4D5 test_frame1.eth_type = 0x0800 test_frame1.ip_version = 4 test_frame1.ip_ihl = 5 test_frame1.ip_dscp = 0 test_frame1.ip_ecn = 0 test_frame1.ip_length = None test_frame1.ip_identification = 0 test_frame1.ip_flags = 2 test_frame1.ip_fragment_offset = 0 test_frame1.ip_ttl = 64 test_frame1.ip_protocol = 0x11 test_frame1.ip_header_checksum = None test_frame1.ip_source_ip = 0xc0a80181 test_frame1.ip_dest_ip = 0xc0a80180 test_frame1.udp_source_port = 1234 test_frame1.udp_dest_port = 14000 test_frame1.payload = pkt1.build_axis() test_frame1.build() test_frame2 = udp_ep.UDPFrame(test_frame1) test_frame2.payload = pkt2.build_axis() test_frame2.build() gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame1.build_eth().build_axis_fcs().data) gmii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame2.build_eth().build_axis_fcs().data) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = gmii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0x13 assert rx_pkt.payload.data == struct.pack('<BH', 0, 4) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = gmii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0x11 assert rx_pkt.payload.data == struct.pack('<BH', 0, 4) + b'\x11\x22\x33\x44' assert gmii_source.empty() assert gmii_sink.empty() yield delay(100) yield clk.posedge print("test 3: enumerate via UART") current_test.next = 3 pkt = xfcp.XFCPFrame() pkt.path = [] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' uart_source.write(pkt.build_axis_cobs().data + b'\x00') yield clk.posedge rx_data = b'' while True: if not uart_sink.empty(): b = bytearray(uart_sink.read(1)) rx_data += b if b[0] == 0: break yield clk.posedge rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis_cobs(rx_data[:-1]) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 64 pkt = xfcp.XFCPFrame() pkt.path = [0] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' uart_source.write(pkt.build_axis_cobs().data + b'\x00') yield clk.posedge rx_data = b'' while True: if not uart_sink.empty(): b = bytearray(uart_sink.read(1)) rx_data += b if b[0] == 0: break yield clk.posedge rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis_cobs(rx_data[:-1]) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [0] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 32 yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters TARGET = "SIM" # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) btn = Signal(intbv(0)[4:]) sw = Signal(intbv(0)[4:]) phy_rx_clk = Signal(bool(0)) phy_rxd = Signal(intbv(0)[4:]) phy_rx_dv = Signal(bool(0)) phy_rx_er = Signal(bool(0)) phy_col = Signal(bool(0)) phy_crs = Signal(bool(0)) uart_rxd = Signal(bool(1)) # Outputs led0_r = Signal(bool(0)) led0_g = Signal(bool(0)) led0_b = Signal(bool(0)) led1_r = Signal(bool(0)) led1_g = Signal(bool(0)) led1_b = Signal(bool(0)) led2_r = Signal(bool(0)) led2_g = Signal(bool(0)) led2_b = Signal(bool(0)) led3_r = Signal(bool(0)) led3_g = Signal(bool(0)) led3_b = Signal(bool(0)) led4 = Signal(bool(0)) led5 = Signal(bool(0)) led6 = Signal(bool(0)) led7 = Signal(bool(0)) phy_tx_clk = Signal(bool(0)) phy_txd = Signal(intbv(0)[4:]) phy_tx_en = Signal(bool(0)) phy_reset_n = Signal(bool(0)) uart_txd = Signal(bool(1)) # sources and sinks mii_source = mii_ep.MIISource() mii_source_logic = mii_source.create_logic(phy_rx_clk, rst, txd=phy_rxd, tx_en=phy_rx_dv, tx_er=phy_rx_er, name='mii_source') mii_sink = mii_ep.MIISink() mii_sink_logic = mii_sink.create_logic(phy_tx_clk, rst, rxd=phy_txd, rx_dv=phy_tx_en, rx_er=False, name='mii_sink') uart_source = uart_ep.UARTSource() uart_source_logic = uart_source.create_logic(clk, rst, txd=uart_rxd, prescale=int(125000000 / (115200 * 8)), name='uart_source') uart_sink = uart_ep.UARTSink() uart_sink_logic = uart_sink.create_logic(clk, rst, rxd=uart_txd, prescale=int(125000000 / (115200 * 8)), name='uart_sink') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, btn=btn, sw=sw, led0_r=led0_r, led0_g=led0_g, led0_b=led0_b, led1_r=led1_r, led1_g=led1_g, led1_b=led1_b, led2_r=led2_r, led2_g=led2_g, led2_b=led2_b, led3_r=led3_r, led3_g=led3_g, led3_b=led3_b, led4=led4, led5=led5, led6=led6, led7=led7, phy_rx_clk=phy_rx_clk, phy_rxd=phy_rxd, phy_rx_dv=phy_rx_dv, phy_rx_er=phy_rx_er, phy_tx_clk=phy_tx_clk, phy_txd=phy_txd, phy_tx_en=phy_tx_en, phy_col=phy_col, phy_crs=phy_crs, phy_reset_n=phy_reset_n, uart_rxd=uart_rxd, uart_txd=uart_txd) @always(delay(4)) def clkgen(): clk.next = not clk phy_clk_hp = Signal(int(40)) @instance def rx_clk_gen(): while True: yield delay(int(phy_clk_hp)) phy_rx_clk.next = not phy_rx_clk phy_tx_clk.next = not phy_tx_clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge # testbench stimulus yield clk.posedge print("test 1: enumerate via UDP") current_test.next = 1 pkt = xfcp.XFCPFrame() pkt.path = [] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' test_frame = udp_ep.UDPFrame() test_frame.eth_dest_mac = 0x020000000000 test_frame.eth_src_mac = 0xDAD1D2D3D4D5 test_frame.eth_type = 0x0800 test_frame.ip_version = 4 test_frame.ip_ihl = 5 test_frame.ip_dscp = 0 test_frame.ip_ecn = 0 test_frame.ip_length = None test_frame.ip_identification = 0 test_frame.ip_flags = 2 test_frame.ip_fragment_offset = 0 test_frame.ip_ttl = 64 test_frame.ip_protocol = 0x11 test_frame.ip_header_checksum = None test_frame.ip_source_ip = 0xc0a80181 test_frame.ip_dest_ip = 0xc0a80180 test_frame.udp_source_port = 1234 test_frame.udp_dest_port = 14000 test_frame.payload = pkt.build_axis() test_frame.build() mii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame.build_eth().build_axis_fcs().data) # wait for ARP request packet rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = mii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = arp_ep.ARPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) assert check_frame.eth_dest_mac == 0xFFFFFFFFFFFF assert check_frame.eth_src_mac == 0x020000000000 assert check_frame.eth_type == 0x0806 assert check_frame.arp_htype == 0x0001 assert check_frame.arp_ptype == 0x0800 assert check_frame.arp_hlen == 6 assert check_frame.arp_plen == 4 assert check_frame.arp_oper == 1 assert check_frame.arp_sha == 0x020000000000 assert check_frame.arp_spa == 0xc0a80180 assert check_frame.arp_tha == 0x000000000000 assert check_frame.arp_tpa == 0xc0a80181 # generate response arp_frame = arp_ep.ARPFrame() arp_frame.eth_dest_mac = 0x020000000000 arp_frame.eth_src_mac = 0xDAD1D2D3D4D5 arp_frame.eth_type = 0x0806 arp_frame.arp_htype = 0x0001 arp_frame.arp_ptype = 0x0800 arp_frame.arp_hlen = 6 arp_frame.arp_plen = 4 arp_frame.arp_oper = 2 arp_frame.arp_sha = 0xDAD1D2D3D4D5 arp_frame.arp_spa = 0xc0a80181 arp_frame.arp_tha = 0x020000000000 arp_frame.arp_tpa = 0xc0a80180 mii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + arp_frame.build_eth().build_axis_fcs().data) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = mii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5 assert check_frame.eth_src_mac == 0x020000000000 assert check_frame.eth_type == 0x0800 assert check_frame.ip_version == 4 assert check_frame.ip_ihl == 5 assert check_frame.ip_dscp == 0 assert check_frame.ip_ecn == 0 assert check_frame.ip_identification == 0 assert check_frame.ip_flags == 2 assert check_frame.ip_fragment_offset == 0 assert check_frame.ip_ttl == 64 assert check_frame.ip_protocol == 0x11 assert check_frame.ip_source_ip == 0xc0a80180 assert check_frame.ip_dest_ip == 0xc0a80181 assert check_frame.udp_source_port == 14000 assert check_frame.udp_dest_port == 1234 rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 64 pkt = xfcp.XFCPFrame() pkt.path = [0] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' test_frame = udp_ep.UDPFrame() test_frame.eth_dest_mac = 0x020000000000 test_frame.eth_src_mac = 0xDAD1D2D3D4D5 test_frame.eth_type = 0x0800 test_frame.ip_version = 4 test_frame.ip_ihl = 5 test_frame.ip_dscp = 0 test_frame.ip_ecn = 0 test_frame.ip_length = None test_frame.ip_identification = 0 test_frame.ip_flags = 2 test_frame.ip_fragment_offset = 0 test_frame.ip_ttl = 64 test_frame.ip_protocol = 0x11 test_frame.ip_header_checksum = None test_frame.ip_source_ip = 0xc0a80181 test_frame.ip_dest_ip = 0xc0a80180 test_frame.udp_source_port = 1234 test_frame.udp_dest_port = 14000 test_frame.payload = pkt.build_axis() test_frame.build() mii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame.build_eth().build_axis_fcs().data) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = mii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) assert check_frame.eth_dest_mac == 0xDAD1D2D3D4D5 assert check_frame.eth_src_mac == 0x020000000000 assert check_frame.eth_type == 0x0800 assert check_frame.ip_version == 4 assert check_frame.ip_ihl == 5 assert check_frame.ip_dscp == 0 assert check_frame.ip_ecn == 0 assert check_frame.ip_identification == 0 assert check_frame.ip_flags == 2 assert check_frame.ip_fragment_offset == 0 assert check_frame.ip_ttl == 64 assert check_frame.ip_protocol == 0x11 assert check_frame.ip_source_ip == 0xc0a80180 assert check_frame.ip_dest_ip == 0xc0a80181 assert check_frame.udp_source_port == 14000 assert check_frame.udp_dest_port == 1234 rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [0] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 32 assert mii_source.empty() assert mii_sink.empty() yield delay(100) yield clk.posedge print("test 1: test write and read RAM 0") current_test.next = 1 pkt1 = xfcp.XFCPFrame() pkt1.path = [0] pkt1.ptype = 0x12 pkt1.payload = bytearray( struct.pack('<BH', 0, 4) + b'\x11\x22\x33\x44') pkt2 = xfcp.XFCPFrame() pkt2.path = [0] pkt2.ptype = 0x10 pkt2.payload = bytearray(struct.pack('<BH', 0, 4)) test_frame1 = udp_ep.UDPFrame() test_frame1.eth_dest_mac = 0x020000000000 test_frame1.eth_src_mac = 0xDAD1D2D3D4D5 test_frame1.eth_type = 0x0800 test_frame1.ip_version = 4 test_frame1.ip_ihl = 5 test_frame1.ip_dscp = 0 test_frame1.ip_ecn = 0 test_frame1.ip_length = None test_frame1.ip_identification = 0 test_frame1.ip_flags = 2 test_frame1.ip_fragment_offset = 0 test_frame1.ip_ttl = 64 test_frame1.ip_protocol = 0x11 test_frame1.ip_header_checksum = None test_frame1.ip_source_ip = 0xc0a80181 test_frame1.ip_dest_ip = 0xc0a80180 test_frame1.udp_source_port = 1234 test_frame1.udp_dest_port = 14000 test_frame1.payload = pkt1.build_axis() test_frame1.build() test_frame2 = udp_ep.UDPFrame(test_frame1) test_frame2.payload = pkt2.build_axis() test_frame2.build() mii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame1.build_eth().build_axis_fcs().data) mii_source.send(b'\x55\x55\x55\x55\x55\x55\x55\xD5' + test_frame2.build_eth().build_axis_fcs().data) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = mii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0x13 assert rx_pkt.payload.data == struct.pack('<BH', 0, 4) rx_frame = None while rx_frame is None: yield clk.posedge rx_frame = mii_sink.recv() check_eth_frame = eth_ep.EthFrame() check_eth_frame.parse_axis_fcs(rx_frame.data[8:]) check_frame = udp_ep.UDPFrame() check_frame.parse_eth(check_eth_frame) print(check_frame) rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis(check_frame.payload.data) print(rx_pkt) assert rx_pkt.ptype == 0x11 assert rx_pkt.payload.data == struct.pack('<BH', 0, 4) + b'\x11\x22\x33\x44' assert mii_source.empty() assert mii_sink.empty() yield delay(100) yield clk.posedge print("test 3: enumerate via UART") current_test.next = 3 pkt = xfcp.XFCPFrame() pkt.path = [] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' uart_source.write(pkt.build_axis_cobs().data + b'\x00') yield clk.posedge rx_data = b'' while True: if not uart_sink.empty(): b = bytearray(uart_sink.read(1)) rx_data += b if b[0] == 0: break yield clk.posedge rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis_cobs(rx_data[:-1]) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 64 pkt = xfcp.XFCPFrame() pkt.path = [0] pkt.rpath = [] pkt.ptype = 0xfe pkt.payload = b'' uart_source.write(pkt.build_axis_cobs().data + b'\x00') yield clk.posedge rx_data = b'' while True: if not uart_sink.empty(): b = bytearray(uart_sink.read(1)) rx_data += b if b[0] == 0: break yield clk.posedge rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis_cobs(rx_data[:-1]) print(rx_pkt) assert rx_pkt.ptype == 0xff assert rx_pkt.path == [0] assert rx_pkt.rpath == [] assert len(rx_pkt.payload.data) == 32 yield delay(100) raise StopSimulation return instances()
def bench(): # Parameters # Inputs clk = Signal(bool(0)) rst = Signal(bool(0)) current_test = Signal(intbv(0)[8:]) uart_rxd = Signal(bool(1)) down_xfcp_in_tdata = Signal(intbv(0)[8:]) down_xfcp_in_tvalid = Signal(bool(0)) down_xfcp_in_tlast = Signal(bool(0)) down_xfcp_in_tuser = Signal(bool(0)) down_xfcp_out_tready = Signal(bool(0)) prescale = Signal(intbv(0)[16:]) # Outputs uart_txd = Signal(bool(1)) down_xfcp_in_tready = Signal(bool(0)) down_xfcp_out_tdata = Signal(intbv(0)[8:]) down_xfcp_out_tvalid = Signal(bool(0)) down_xfcp_out_tlast = Signal(bool(0)) down_xfcp_out_tuser = Signal(bool(0)) # sources and sinks uart_source = uart_ep.UARTSource() uart_source_logic = uart_source.create_logic(clk, rst, txd=uart_rxd, prescale=prescale, name='uart_source') uart_sink = uart_ep.UARTSink() uart_sink_logic = uart_sink.create_logic(clk, rst, rxd=uart_txd, prescale=prescale, name='uart_sink') # XFCP ports down_xfcp_port = xfcp.XFCPPort() down_xfcp_port_logic = down_xfcp_port.create_logic( clk=clk, rst=rst, xfcp_in_tdata=down_xfcp_out_tdata, xfcp_in_tvalid=down_xfcp_out_tvalid, xfcp_in_tready=down_xfcp_out_tready, xfcp_in_tlast=down_xfcp_out_tlast, xfcp_in_tuser=down_xfcp_out_tuser, xfcp_out_tdata=down_xfcp_in_tdata, xfcp_out_tvalid=down_xfcp_in_tvalid, xfcp_out_tready=down_xfcp_in_tready, xfcp_out_tlast=down_xfcp_in_tlast, xfcp_out_tuser=down_xfcp_in_tuser, name='down_xfcp_port') # DUT if os.system(build_cmd): raise Exception("Error running build command") dut = Cosimulation("vvp -m myhdl %s.vvp -lxt2" % testbench, clk=clk, rst=rst, current_test=current_test, uart_rxd=uart_rxd, uart_txd=uart_txd, down_xfcp_in_tdata=down_xfcp_in_tdata, down_xfcp_in_tvalid=down_xfcp_in_tvalid, down_xfcp_in_tready=down_xfcp_in_tready, down_xfcp_in_tlast=down_xfcp_in_tlast, down_xfcp_in_tuser=down_xfcp_in_tuser, down_xfcp_out_tdata=down_xfcp_out_tdata, down_xfcp_out_tvalid=down_xfcp_out_tvalid, down_xfcp_out_tready=down_xfcp_out_tready, down_xfcp_out_tlast=down_xfcp_out_tlast, down_xfcp_out_tuser=down_xfcp_out_tuser, prescale=prescale) @always(delay(4)) def clkgen(): clk.next = not clk @instance def check(): yield delay(100) yield clk.posedge rst.next = 1 yield clk.posedge rst.next = 0 yield clk.posedge yield delay(100) yield clk.posedge prescale.next = 1 # testbench stimulus yield clk.posedge print("test 1: receive") current_test.next = 1 pkt = xfcp.XFCPFrame() pkt.path = [1, 2, 3] pkt.rpath = [4] pkt.ptype = 1 pkt.payload = bytearray(range(32)) uart_source.write(pkt.build_axis_cobs().data + b'\x00') rx_pkt = None while rx_pkt is None: yield clk.posedge rx_pkt = down_xfcp_port.recv() print(rx_pkt) assert rx_pkt == pkt yield delay(100) yield clk.posedge print("test 2: transmit") current_test.next = 2 pkt = xfcp.XFCPFrame() pkt.path = [1, 2, 3] pkt.rpath = [4] pkt.ptype = 1 pkt.payload = bytearray(range(32)) down_xfcp_port.send(pkt) yield clk.posedge rx_data = b'' while True: if not uart_sink.empty(): b = bytearray(uart_sink.read(1)) rx_data += b if b[0] == 0: break yield clk.posedge rx_pkt = xfcp.XFCPFrame() rx_pkt.parse_axis_cobs(rx_data[:-1]) print(rx_pkt) assert rx_pkt == pkt yield delay(100) raise StopSimulation return instances()