def __init__(self,
platform,
connector="pcie",
with_etherbone=False,
with_analyzer=False):
sys_clk_freq = int(125e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="USB3SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Serial Bridge ----------------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq)
self.add_wb_master(self.bridge.wishbone)
# Ethernet <--> Wishbone -------------------------------------------------------------------
if with_etherbone:
# phy
self.submodules.eth_phy = LiteEthPHYRGMII(
clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"))
self.add_csr("eth_phy")
# core
self.submodules.eth_core = LiteEthUDPIPCore(
phy=self.eth_phy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.50",
clk_freq=sys_clk_freq)
# etherbone
self.submodules.etherbone = LiteEthEtherbone(
self.eth_core.udp, 1234)
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
# USB3 SerDes ------------------------------------------------------------------------------
usb3_serdes = ECP5USB3SerDes(
platform,
sys_clk=self.crg.cd_sys.clk,
sys_clk_freq=sys_clk_freq,
refclk_pads=ClockSignal("clk200"),
refclk_freq=200e6,
tx_pads=platform.request(connector + "_tx"),
rx_pads=platform.request(connector + "_rx"),
channel=1 if connector == "sma" else 0)
self.submodules += usb3_serdes
# USB3 PIPE --------------------------------------------------------------------------------
usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules.usb3_pipe = usb3_pipe
self.comb += usb3_pipe.reset.eq(~platform.request("rst_n"))
# USB3 Core --------------------------------------------------------------------------------
usb3_core = USB3Core(platform)
self.submodules.usb3_core = usb3_core
self.comb += [
usb3_pipe.source.connect(usb3_core.sink),
usb3_core.source.connect(usb3_pipe.sink),
usb3_core.reset.eq(~usb3_pipe.ready),
]
self.add_csr("usb3_core")
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(~usb3_serdes.ready)
self.comb += platform.request("user_led", 1).eq(~usb3_pipe.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# LFPS
usb3_serdes.tx_idle,
usb3_serdes.rx_idle,
usb3_serdes.tx_pattern,
usb3_serdes.rx_polarity,
usb3_pipe.lfps.rx_polling,
usb3_pipe.lfps.tx_polling,
# Training Sequence
usb3_pipe.ts.tx_enable,
usb3_pipe.ts.rx_ts1,
usb3_pipe.ts.rx_ts2,
usb3_pipe.ts.tx_enable,
usb3_pipe.ts.tx_tseq,
usb3_pipe.ts.tx_ts1,
usb3_pipe.ts.tx_ts2,
usb3_pipe.ts.tx_done,
# LTSSM
usb3_pipe.ltssm.polling.fsm,
usb3_pipe.ready,
# Endpoints
usb3_serdes.rx_datapath.skip_remover.skip,
usb3_serdes.source,
usb3_serdes.sink,
usb3_pipe.source,
usb3_pipe.sink,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
self.add_csr("analyzer")
def __init__(self, platform, with_analyzer=False):
sys_clk_freq = int(150e6)
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="USB3SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Serial bridge ----------------------------------------------------------------------------
self.submodules.serial_bridge = UARTWishboneBridge(
platform.request("serial"), sys_clk_freq)
self.add_wb_master(self.serial_bridge.wishbone)
# USB3 SerDes ------------------------------------------------------------------------------
usb3_serdes = A7USB3SerDes(platform,
sys_clk=self.crg.cd_sys.clk,
sys_clk_freq=sys_clk_freq,
refclk_pads=ClockSignal("clk125"),
refclk_freq=125e6,
tx_pads=platform.request("pcie_tx"),
rx_pads=platform.request("pcie_rx"))
self.submodules += usb3_serdes
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# USB3 PIPE --------------------------------------------------------------------------------
usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules.usb3_pipe = usb3_pipe
self.comb += usb3_pipe.reset.eq(~platform.request("user_btn", 0))
# USB3 Core --------------------------------------------------------------------------------
usb3_core = USB3Core(platform)
self.submodules.usb3_core = usb3_core
self.comb += [
usb3_pipe.source.connect(usb3_core.sink),
usb3_core.source.connect(usb3_pipe.sink),
usb3_core.reset.eq(~usb3_pipe.ready),
]
self.add_csr("usb3_core")
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)
self.comb += platform.request("user_led", 1).eq(usb3_pipe.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# LFPS
usb3_serdes.tx_idle,
usb3_serdes.rx_idle,
usb3_serdes.tx_pattern,
usb3_serdes.rx_polarity,
usb3_pipe.lfps.rx_polling,
usb3_pipe.lfps.tx_polling,
# Training Sequence
usb3_pipe.ts.tx_enable,
usb3_pipe.ts.rx_ts1,
usb3_pipe.ts.rx_ts2,
usb3_pipe.ts.tx_enable,
usb3_pipe.ts.tx_tseq,
usb3_pipe.ts.tx_ts1,
usb3_pipe.ts.tx_ts2,
usb3_pipe.ts.tx_done,
# LTSSM
usb3_pipe.ltssm.polling.fsm,
usb3_pipe.ready,
# Endpoints
usb3_serdes.rx_datapath.skip_remover.skip,
usb3_serdes.source,
usb3_serdes.sink,
usb3_pipe.source,
usb3_pipe.sink,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
platform,
connector="sfp",
with_etherbone=True,
with_analyzer=True):
sys_clk_freq = int(125e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="USB3SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# UARTBone ---------------------------------------------------------------------------------
self.add_uartbone()
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.eth_phy = LiteEthPHY(
clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"),
clk_freq=sys_clk_freq)
self.add_etherbone(phy=self.eth_phy, ip_address="192.168.1.50")
# USB3 SerDes ------------------------------------------------------------------------------
usb3_serdes = K7USB3SerDes(platform,
sys_clk=self.crg.cd_sys.clk,
sys_clk_freq=sys_clk_freq,
refclk_pads=ClockSignal("clk125"),
refclk_freq=125e6,
tx_pads=platform.request(connector + "_tx"),
rx_pads=platform.request(connector + "_rx"))
self.submodules += usb3_serdes
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# USB3 PIPE --------------------------------------------------------------------------------
usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules.usb3_pipe = usb3_pipe
self.comb += usb3_pipe.reset.eq(platform.request("cpu_reset"))
# USB3 Core --------------------------------------------------------------------------------
usb3_core = USB3Core(platform)
self.submodules.usb3_core = usb3_core
self.comb += [
usb3_pipe.source.connect(usb3_core.sink),
usb3_core.source.connect(usb3_pipe.sink),
usb3_core.reset.eq(~usb3_pipe.ready),
]
# Debug IOs (Through CYUSB3ACC-005) --------------------------------------------------------
_debug_ios = [
("tx_idle", 0, Pins("AK20"), IOStandard("LVCMOS12")), # I2C_SDA
("rx_idle", 0, Pins("AK21"), IOStandard("LVCMOS12")), # I2C_SCL
]
self.platform.add_extension(_debug_ios)
self.comb += [
platform.request("tx_idle").eq(usb3_serdes.tx_idle),
platform.request("rx_idle").eq(usb3_serdes.rx_idle),
]
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)
self.comb += platform.request("user_led", 1).eq(usb3_pipe.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# LFPS
usb3_serdes.tx_idle,
usb3_serdes.rx_idle,
usb3_serdes.tx_pattern,
usb3_serdes.rx_polarity,
usb3_pipe.lfps.rx_polling,
usb3_pipe.lfps.tx_polling,
# Training Sequence
usb3_pipe.ts.tx_enable,
usb3_pipe.ts.rx_ts1,
usb3_pipe.ts.rx_ts2,
usb3_pipe.ts.tx_enable,
usb3_pipe.ts.tx_tseq,
usb3_pipe.ts.tx_ts1,
usb3_pipe.ts.tx_ts2,
usb3_pipe.ts.tx_done,
# LTSSM
usb3_pipe.ltssm.polling.fsm,
usb3_pipe.ready,
# Endpoints
usb3_serdes.rx_datapath.skip_remover.skip,
usb3_serdes.source,
usb3_serdes.sink,
usb3_pipe.source,
usb3_pipe.sink,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 4096, csr_csv="analyzer.csv")
def __init__(self, phy_dw=20):
platform = Platform()
sys_clk_freq = int(133e6)
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq)
# USB3 Host
host_usb3_serdes = USB3SerDesModel(phy_dw=phy_dw)
host_usb3_pipe = USB3PIPE(serdes=host_usb3_serdes,
sys_clk_freq=sys_clk_freq,
with_scrambling=True)
self.submodules += host_usb3_serdes, host_usb3_pipe
host_usb3_pipe.finalize()
host_usb3_core = USB3Core(platform)
self.submodules.host_usb3_core = host_usb3_core
self.comb += [
host_usb3_serdes.tx_polarity.eq(
1), # Inverse TX polarity to test RX auto-polarity
host_usb3_pipe.source.connect(host_usb3_core.sink),
host_usb3_core.source.connect(host_usb3_pipe.sink),
host_usb3_core.reset.eq(~host_usb3_pipe.ready),
]
self.add_csr("host_usb3_core")
# USB3 Device
dev_usb3_serdes = USB3SerDesModel(phy_dw=phy_dw)
dev_usb3_pipe = USB3PIPE(serdes=dev_usb3_serdes,
sys_clk_freq=sys_clk_freq,
with_scrambling=True)
self.submodules += dev_usb3_serdes, dev_usb3_pipe
dev_usb3_pipe.finalize()
dev_usb3_core = USB3Core(platform)
self.submodules.dev_usb3_core = dev_usb3_core
self.comb += [
dev_usb3_serdes.tx_polarity.eq(
1), # Inverse TX polarity to test RX auto-polarity
dev_usb3_pipe.source.connect(dev_usb3_core.sink),
dev_usb3_core.source.connect(dev_usb3_pipe.sink),
dev_usb3_core.reset.eq(~dev_usb3_pipe.ready),
]
self.add_csr("dev_usb3_core")
# Connect Host <--> Device
self.comb += host_usb3_serdes.connect(dev_usb3_serdes)
# Simulation Timer
timer = Signal(32)
self.sync += timer.eq(timer + 1)
# Simulation Status
for pipe, fsm in [["host", host_usb3_pipe.ltssm.polling.fsm],
["dev ", dev_usb3_pipe.ltssm.polling.fsm]]:
for state, value in fsm.encoding.items():
self.sync += [
If(
fsm.next_state != fsm.state,
If(
fsm.next_state == value,
Display(
"[%08d] {} entering {} state".format(
pipe.upper(), state), timer)))
]
# Simulation End
end_timer = WaitTimer(2**16)
self.submodules += end_timer
self.comb += end_timer.wait.eq(host_usb3_pipe.ready
& dev_usb3_pipe.ready)
self.sync += If(end_timer.done, Finish())
def __init__(self,
platform,
connector="pcie",
with_etherbone=False,
with_analyzer=False):
sys_clk_freq = int(125e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="USB3SoC",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# UARTBone ---------------------------------------------------------------------------------
self.add_uartbone()
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.eth_phy = LiteEthPHYRGMII(
clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"))
self.add_etherbone(phy=self.eth_phy, ip_address="192.168.1.50")
# USB3 SerDes ------------------------------------------------------------------------------
usb3_serdes = ECP5USB3SerDes(
platform,
sys_clk=self.crg.cd_sys.clk,
sys_clk_freq=sys_clk_freq,
refclk_pads=ClockSignal("clk250"),
refclk_freq=250e6,
tx_pads=platform.request(connector + "_tx"),
rx_pads=platform.request(connector + "_rx"),
channel=1 if connector == "sma" else 0)
self.submodules += usb3_serdes
# USB3 PIPE --------------------------------------------------------------------------------
usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules.usb3_pipe = usb3_pipe
self.comb += usb3_pipe.reset.eq(~platform.request("rst_n"))
# USB3 Core --------------------------------------------------------------------------------
usb3_core = USB3Core(platform)
self.submodules.usb3_core = usb3_core
self.comb += [
usb3_pipe.source.connect(usb3_core.sink),
usb3_core.source.connect(usb3_pipe.sink),
usb3_core.reset.eq(~usb3_pipe.ready),
]
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(~usb3_serdes.ready)
self.comb += platform.request("user_led", 1).eq(~usb3_pipe.ready)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# LFPS
usb3_serdes.tx_idle,
usb3_serdes.rx_idle,
usb3_serdes.tx_pattern,
usb3_serdes.rx_polarity,
usb3_pipe.lfps.rx_polling,
usb3_pipe.lfps.tx_polling,
# Training Sequence
usb3_pipe.ts.tx_enable,
usb3_pipe.ts.rx_ts1,
usb3_pipe.ts.rx_ts2,
usb3_pipe.ts.tx_enable,
usb3_pipe.ts.tx_tseq,
usb3_pipe.ts.tx_ts1,
usb3_pipe.ts.tx_ts2,
usb3_pipe.ts.tx_done,
# LTSSM
usb3_pipe.ltssm.polling.fsm,
usb3_pipe.ready,
# Endpoints
usb3_serdes.rx_datapath.skip_remover.skip,
usb3_serdes.source,
usb3_serdes.sink,
usb3_pipe.source,
usb3_pipe.sink,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 4096, csr_csv="tools/analyzer.csv")