def main():
parser = argparse.ArgumentParser(
description=
'Convert FPGA configuration description ("FPGA assembly") into binary frame equivalent'
)
util.db_root_arg(parser)
util.part_arg(parser)
parser.add_argument('--sparse',
action='store_true',
help="Don't zero fill all frames")
parser.add_argument(
'--roi',
help="ROI design.json file defining which tiles are within the ROI.")
parser.add_argument('--debug',
action='store_true',
help="Print debug dump")
parser.add_argument('--dump_bits',
action='store_true',
help="Output in bits format (bit_%08x_%03d_%02d)")
parser.add_argument('fn_in', help='Input FPGA assembly (.fasm) file')
parser.add_argument('fn_out',
default='/dev/stdout',
nargs='?',
help='Output FPGA frame (.frm) file')
args = parser.parse_args()
run(db_root=args.db_root,
part=args.part,
filename_in=args.fn_in,
f_out=open(args.fn_out, 'w'),
sparse=args.sparse,
roi=args.roi,
dump_bits=args.dump_bits,
debug=args.debug)
def main():
import argparse
parser = argparse.ArgumentParser(
description="Parse a db repository, checking for consistency")
util.db_root_arg(parser)
util.part_arg(parser)
parser.add_argument('--verbose', action='store_true', help='')
args = parser.parse_args()
run(args.db_root, args.part, verbose=args.verbose)
def main():
parser = argparse.ArgumentParser()
util.db_root_arg(parser)
util.part_arg(parser)
parser.add_argument('input')
args = parser.parse_args()
db = Database(args.db_root, args.part)
grid = db.grid()
base_address_to_tiles = {}
for tile in grid.tiles():
gridinfo = grid.gridinfo_at_tilename(tile)
if BlockType.CLB_IO_CLK in gridinfo.bits:
base_address = gridinfo.bits[BlockType.CLB_IO_CLK].base_address
if base_address not in base_address_to_tiles:
base_address_to_tiles[base_address] = []
base_address_to_tiles[base_address].append(
(tile, gridinfo.bits[BlockType.CLB_IO_CLK]))
for line in fasm.parse_fasm_filename(args.input):
is_unknown = False
annotation_data = {}
for annotation in line.annotations:
annotation_data[annotation.name] = annotation.value
if 'unknown_bit' not in annotation_data:
continue
base_address = int(annotation_data['unknown_segment'], 0)
frame_offset = int(annotation_data['unknown_segbit'].split('_')[0])
bit = int(annotation_data['unknown_segbit'].split('_')[1])
offset = bit // 16
if base_address not in base_address_to_tiles:
print('# No tile for base address')
else:
for tile, bits in base_address_to_tiles[base_address]:
if offset >= bits.offset and offset - bits.offset < bits.words:
print('# {} : {:02d}_{:02d}'.format(
tile, frame_offset,
bit - bitstream.WORD_SIZE_BITS * bits.offset))
for l in fasm.fasm_line_to_string(line):
print(l)
def main():
parser = argparse.ArgumentParser(
description=__doc__,
formatter_class=argparse.RawDescriptionHelpFormatter)
util.db_root_arg(parser)
parser.add_argument(
'--seg-fn-in', required=True, help='Input segbits db file')
parser.add_argument(
'--seg-fn-out', required=True, help='Output segbits db file')
parser.add_argument(
'--zero-db',
default=None,
help='Input file name with zero group(s) definitions')
parser.add_argument(
"-g",
"--groups",
type=str,
default=None,
help="Input tag group definition file")
parser.add_argument(
'--strict', action='store_true', help='Strict db checks')
parser.add_argument(
'--filter_across_groups',
help='Filter out bits that match between groups',
action='store_true')
parser.add_argument(
'--verbose', action='store_true', help='Be more verbose')
args = parser.parse_args()
run(args.db_root,
args.zero_db,
args.seg_fn_in,
args.seg_fn_out,
args.groups,
args.filter_across_groups,
strict=args.strict,
verbose=args.verbose)
def main():
import argparse
parser = argparse.ArgumentParser(description="Combine multiple .db files")
util.db_root_arg(parser)
parser.add_argument('--verbose', action='store_true', help='')
parser.add_argument('--track_origin', action='store_true', help='')
parser.add_argument('--out', help='')
parser.add_argument('ins', nargs='+', help='Last takes precedence')
args = parser.parse_args()
run(args.ins,
args.out,
strict=int(os.getenv("MERGEDB_STRICT", "1")),
track_origin=args.track_origin,
verbose=args.verbose)
def main():
parser = argparse.ArgumentParser(
description="Tool for checking which tiles have bits defined.")
util.db_root_arg(parser)
util.part_arg(parser)
parser.add_argument('--show-only-missing', action='store_true')
parser.add_argument('--verbose', action='store_true')
args = parser.parse_args()
db = Database(args.db_root, args.part)
grid = db.grid()
tile_types = {}
for tile in grid.tiles():
gridinfo = grid.gridinfo_at_tilename(tile)
if gridinfo.tile_type not in tile_types:
tile_types[gridinfo.tile_type] = []
tile_types[gridinfo.tile_type].append((tile, gridinfo))
total_tile_count = 0
total_have_bits = 0
for tile_type, tiles in sorted(tile_types.items()):
try:
tile_type_info = db.get_tile_type(tile_type)
# Skip empty tiles, as no base address is requied.
if len(tile_type_info.get_pips()) == 0 and len(
tile_type_info.get_sites()) == 0:
continue
except KeyError:
pass
# INT_INTERFACE tiles likely don't contain configuration? Remove this
# if this ends up false.
if 'INT_INTERFACE' in tile_type:
continue
if 'BRKH' in tile_type:
continue
have_bits = 0
for tile_name, gridinfo in tiles:
total_tile_count += 1
if BlockType.CLB_IO_CLK in gridinfo.bits:
have_bits += 1
total_have_bits += 1
if args.show_only_missing and have_bits == len(tiles):
continue
print('{}: {}/{} ({:.2f} %)'.format(
tile_type, have_bits, len(tiles),
100. * float(have_bits) / len(tiles)))
if args.verbose:
tiles_with_missing_bits = []
for tile_name, gridinfo in tiles:
total_tile_count += 1
if BlockType.CLB_IO_CLK not in gridinfo.bits:
tiles_with_missing_bits.append(tile_name)
for tile_name in sorted(tiles_with_missing_bits):
print('{} is missing CLB_IO_CLK'.format(tile_name))
print('')
print('Summary: {}/{} ({:.2f} %)'.format(
total_have_bits, total_tile_count,
100. * float(total_have_bits) / total_tile_count))
def main():
parser = argparse.ArgumentParser(
description=
'Convert FPGA configuration description ("FPGA assembly") into bitstream.'
)
util.db_root_arg(parser)
util.part_arg(parser)
parser.add_argument(
'--sparse', action='store_true', help="Don't zero fill all frames")
parser.add_argument(
'--frames-file',
help=
'Output filename for frame data output, default is deleted tempfile.',
default=None)
parser.add_argument(
'--bits-file',
help=
'Output filename for frame data output, default is deleted tempfile.',
default=None)
parser.add_argument('fn_in', help='Input FPGA assembly (.fasm) file')
parser.add_argument('fn_out', help='Output FPGA bitstream (.bit) file')
if os.getenv("URAY_ARCH") is None:
default_arch = "UltraScale"
else:
default_arch = os.getenv("URAY_ARCH")
parser.add_argument(
'--architecture',
help=
"Name of the device architecture family (e.g. UltraScale, Series7, etc.)",
default=default_arch)
if os.getenv("URAY_TOOLS_DIR") is None:
default_xcframes2bit = 'xcframes2bit'
else:
default_xcframes2bit = os.path.join(
os.getenv("URAY_TOOLS_DIR"), 'xcframes2bit')
parser.add_argument(
'--xcframes2bit',
help="Path to xcframes2bit executable.",
default=default_xcframes2bit)
args = parser.parse_args()
with contextlib.ExitStack() as stack:
if args.frames_file:
frames_file = stack.enter_context(open(args.frames_file, 'w'))
else:
frames_file = stack.enter_context(tempfile.NamedTemporaryFile())
if args.bits_file:
bits_file = stack.enter_context(open(args.bits_file, 'w'))
else:
bits_file = None
fasm_to_frames(
db_root=args.db_root,
part=args.part,
filename_in=args.fn_in,
sparse=args.sparse,
frames_file=frames_file,
bits_file=bits_file,
)
frames_to_bit(
xcframes2bit=args.xcframes2bit,
arch=args.architecture,
part=args.part,
part_yaml=os.path.join(args.db_root, args.part, "part.yaml"),
frames_filename=frames_file.name,
bit_filename=args.fn_out)
