def test_wmp_scenario1(rambank, chip):
    """Test WMP instruction functionality."""
    import random

    chip_test = Processor()
    chip_base = Processor()

    value = random.randint(0, 15)  # Select a random value

    # Perform the instruction under test:
    chip_test.PROGRAM_COUNTER = 0
    chip_test.CURRENT_RAM_BANK = rambank
    chip_test.set_accumulator(value)
    chip_test.COMMAND_REGISTER = \
        encode_command_register(chip, 0, 0, 'RAM_PORT')
    Processor.wmp(chip_test)

    # Simulate conditions at end of instruction in base chip
    chip_base.PROGRAM_COUNTER = 0
    chip_base.set_accumulator(value)
    chip_base.COMMAND_REGISTER = \
        encode_command_register(chip, 0, 0, 'RAM_PORT')
    chip_base.increment_pc(1)
    chip_base.CURRENT_RAM_BANK = rambank
    chip_base.RAM_PORT[rambank][chip] = chip_base.ACCUMULATOR

    # Make assertions that the base chip is now at the same state as
    # the test chip which has been operated on by the instruction under test.

    assert chip_test.read_program_counter() == chip_base.read_program_counter()
    assert chip_test.read_accumulator() == chip_base.read_accumulator()

    # Pickling each chip and comparing will show equality or not.
    assert pickle.dumps(chip_test) == pickle.dumps(chip_base)
def test_rdr_scenario1(values):
    """Test RDM instruction functionality."""
    chip_test = Processor()
    chip_base = Processor()

    # Perform the instruction under test:

    chip_test.set_accumulator(0)
    chip_test.COMMAND_REGISTER = \
        encode_command_register(values[0], 0, 0, 'ROM_PORT')
    chip_test.ROM_PORT[values[0]] = values[1]
    Processor.rdr(chip_test)

    # Simulate conditions at end of instruction in base chip
    chip_base.COMMAND_REGISTER = \
        encode_command_register(values[0], 0, 0, 'ROM_PORT')
    chip_base.ROM_PORT[values[0]] = values[1]
    chip_base.set_accumulator(values[1])
    chip_base.increment_pc(1)

    # Make assertions that the base chip is now at the same state as
    # the test chip which has been operated on by the instruction under test.

    assert chip_test.read_program_counter() == chip_base.read_program_counter()
    assert chip_test.read_accumulator() == chip_base.read_accumulator()

    # Pickling each chip and comparing will show equality or not.
    assert pickle.dumps(chip_test) == pickle.dumps(chip_base)
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def test_wrm_scenario1(rambank, chip, register, address):
    """Test WRM instruction functionality."""
    import random

    chip_test = Processor()
    chip_base = Processor()

    value = random.randint(0, 15)  # Select a random value

    # Perform the instruction under test:
    chip_test.PROGRAM_COUNTER = 0
    chip_test.CURRENT_RAM_BANK = rambank
    absolute_address = convert_to_absolute_address(chip_test, rambank, chip,
                                                   register, address)
    chip_test.set_accumulator(value)
    chip_test.COMMAND_REGISTER = \
        encode_command_register(chip, register, address, 'DATA_RAM_CHAR')
    Processor.wrm(chip_test)

    # Simulate conditions at end of instruction in base chip
    chip_base.PROGRAM_COUNTER = 0
    chip_base.RAM[absolute_address] = value
    chip_base.set_accumulator(value)
    chip_base.COMMAND_REGISTER = \
        encode_command_register(chip, register, address, 'DATA_RAM_CHAR')
    chip_base.increment_pc(1)
    chip_base.CURRENT_RAM_BANK = rambank

    # Make assertions that the base chip is now at the same state as
    # the test chip which has been operated on by the instruction under test.
    assert chip_test.read_program_counter() == chip_base.read_program_counter()
    assert chip_test.read_accumulator() == chip_base.read_accumulator()

    # Pickling each chip and comparing will show equality or not.
    assert pickle.dumps(chip_test) == pickle.dumps(chip_base)
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def common_wpm_code_1(desired_chip: Processor, chip: Processor,
                      rambank: int, register: int, address: int,
                      reg_pair_first: int,
                      reg_pair_second: int) -> Tuple[str, str]:
    """Common code applicable to all tests to reduce duplication."""
    # Line a
    desired_chip.COMMAND_REGISTER = \
        encode_command_register(chip, register, address, 'DATA_RAM_CHAR')

    address_to_write_to = convert_to_absolute_address(
        desired_chip, rambank, chip, register, address)
    chunks = c2n(12, 4, address_to_write_to, 'b')

    # Lines b - d    # Store middle bits in register "reg_pair_first"
    desired_chip.STATUS_CHARACTERS[rambank][0][0][1] = \
        binary_to_decimal(str(chunks[1]))
    desired_chip.REGISTERS[reg_pair_first] = \
        desired_chip.STATUS_CHARACTERS[rambank][0][0][1]

    # Lines e - g   # Store lower bits in register "reg_pair_second"
    desired_chip.STATUS_CHARACTERS[rambank][0][0][2] = \
        binary_to_decimal(str(chunks[2]))
    desired_chip.REGISTERS[reg_pair_second] = \
        desired_chip.STATUS_CHARACTERS[rambank][0][0][2]

    # Lines h - j    # Store higher bits in ROM PORT 15
    desired_chip.STATUS_CHARACTERS[rambank][0][0][0] = \
        binary_to_decimal(str(chunks[0]))
    desired_chip.ROM_PORT[15] = \
        desired_chip.STATUS_CHARACTERS[rambank][0][0][0]
    return chunks, address_to_write_to
def test_adm_scenario1(values):
    """Test ADM instruction functionality."""
    chip_test = Processor()
    chip_base = Processor()

    rambank = values[0]
    chip = values[1]
    register = values[2]
    address = values[3]
    value = values[4]
    accumulator = 2

    cr = encode_command_register(chip, register, address, 'DATA_RAM_CHAR')

    chip_test.CARRY = 0
    chip_test.COMMAND_REGISTER = cr

    chip_test.CURRENT_RAM_BANK = rambank
    absolute_address = convert_to_absolute_address(
        chip_test, rambank, chip, register, address)
    chip_test.RAM[absolute_address] = value
    chip_test.set_accumulator(accumulator)

    Processor.adm(chip_test)

    # Simulate conditions at end of instruction in base chip
    chip_base.CARRY = 0
    chip_base.COMMAND_REGISTER = cr
    absolute_address = convert_to_absolute_address(
        chip_base, rambank, chip, register, address)
    chip_base.RAM[absolute_address] = value
    chip_base.increment_pc(1)
    chip_base.CURRENT_RAM_BANK = rambank
    chip_base.set_accumulator(value + accumulator)

    # Make assertions that the base chip is now at the same state as
    # the test chip which has been operated on by the instruction under test.

    assert chip_test.read_program_counter() == chip_base.read_program_counter()
    assert chip_test.read_accumulator() == chip_base.read_accumulator()

    # Pickling each chip and comparing will show equality or not.
    assert pickle.dumps(chip_test) == pickle.dumps(chip_base)
def test_adm_scenario1(rambank, chip, register, address, value,
                       accumulator, carry):
    """Test ADM instruction functionality."""
    chip_test = Processor()
    chip_base = Processor()

    cr = encode_command_register(chip, register, address, 'DATA_RAM_CHAR')

    chip_test.CARRY = carry
    chip_test.COMMAND_REGISTER = cr

    chip_test.CURRENT_RAM_BANK = rambank
    absolute_address = convert_to_absolute_address(
        chip_test, rambank, chip, register, address)
    chip_test.RAM[absolute_address] = value
    chip_test.set_accumulator(accumulator)

    Processor.sbm(chip_test)

    # Simulate conditions at end of instruction in base chip

    chip_base.CARRY = carry
    chip_base.COMMAND_REGISTER = cr
    absolute_address = convert_to_absolute_address(
        chip_base, rambank, chip, register, address)
    chip_base.RAM[absolute_address] = value
    chip_base.increment_pc(1)
    chip_base.CURRENT_RAM_BANK = rambank
    chip_base.set_accumulator(accumulator)
    value_complement = int(ones_complement(value, 4), 2)
    carry_complement = chip_base.read_complement_carry()
    chip_base.ACCUMULATOR = (chip_base.ACCUMULATOR + value_complement +
                             carry_complement)
    Processor.check_overflow(chip_base)
    # Make assertions that the base chip is now at the same state as
    # the test chip which has been operated on by the instruction under test.

    assert chip_test.read_program_counter() == chip_base.read_program_counter()
    assert chip_test.read_accumulator() == chip_base.read_accumulator()

    # Pickling each chip and comparing will show equality or not.
    assert pickle.dumps(chip_test) == pickle.dumps(chip_base)
def test_wrn_scenario1(rambank, chip, register, char):
    """Test instruction WRn"""
    from random import randint

    chip_test = Processor()
    chip_base = Processor()

    value = randint(0, 15)

    address = encode_command_register(chip, register, 0,
                                      'DATA_RAM_STATUS_CHAR')
    chip_test.CURRENT_RAM_BANK = rambank
    chip_test.COMMAND_REGISTER = address
    chip_test.set_accumulator(value)

    # Perform the instruction under test:
    if char == 0:
        Processor.wr0(chip_test)
    if char == 1:
        Processor.wr1(chip_test)
    if char == 2:
        Processor.wr2(chip_test)
    if char == 3:
        Processor.wr3(chip_test)

    # Simulate conditions at end of instruction in base chip
    chip_base.COMMAND_REGISTER = address
    chip_base.CURRENT_RAM_BANK = rambank
    chip_base.increment_pc(1)
    chip_base.set_accumulator(value)
    chip_base.STATUS_CHARACTERS[rambank][chip][register][char] = value

    # Make assertions that the base chip is now at the same state as
    # the test chip which has been operated on by the instruction under test.

    assert chip_test.read_program_counter() == chip_base.read_program_counter()
    assert chip_test.read_accumulator() == chip_base.read_accumulator()

    # Pickling each chip and comparing will show equality or not.
    assert pickle.dumps(chip_test) == pickle.dumps(chip_base)