def run_steps(self):
self.backend.build_main(self.top + '.eblif')
self.backend.build_main(self.top + '.net')
self.backend.build_main(self.top + '.place')
self.backend.build_main(self.top + '.route')
self.backend.build_main(self.top + '.fasm')
with Timed(self, 'bitstream'):
self.backend.build_main(self.top + '.bit')
with Timed(self, 'fasm2bels'):
self.backend.build_main('timing_summary.rpt')
def run(self):
with Timed(self, 'prepare'):
os.makedirs(self.out_dir, exist_ok=True)
for f in self.srcs:
if f.endswith(".vhd") or f.endswith(".vhdl"):
self.files.append({
'name': os.path.realpath(f),
'file_type': 'vhdlSource'
})
elif f.endswith(".v"):
self.files.append({
'name': os.path.realpath(f),
'file_type': 'verilogSource'
})
self.files.append({
'name': os.path.realpath(self.xdc),
'file_type': 'xdc'
})
chip = self.family + self.device + self.package
vivado_settings = os.getenv('VIVADO_SETTINGS')
self.edam = {
'files': self.files,
'name': self.project_name,
'toplevel': self.top,
'parameters': {
'VIVADO': {
'paramtype': 'vlogdefine',
'datatype': 'int',
'default': 1,
},
},
'tool_options': {
'vivado': {
'part': chip,
'synth': self.synthtool,
'vivado-settings': vivado_settings,
'yosys_synth_options': self.synthoptions,
}
}
}
self.backend = edalize.get_edatool('vivado')(
edam=self.edam, work_root=self.out_dir)
self.backend.configure("")
with Timed(self, 'total'):
self.backend.build()
self.add_runtimes()
self.add_maximum_memory_use()
def run_steps(self):
self.backend.build_main(self.top + '.eblif')
with Timed(self, 'pack_all', unprinted_runtime=True):
self.backend.build_main(self.top + '.net')
with Timed(self, 'place_all', unprinted_runtime=True):
self.backend.build_main(self.top + '.place')
with Timed(self, 'route_all', unprinted_runtime=True):
self.backend.build_main(self.top + '.route')
self.backend.build_main(self.top + '.fasm')
with Timed(self, 'bitstream'):
self.backend.build_main(self.top + '.bit')
def __init__(self, rootdir):
self.rootdir = rootdir
self.runtimes = collections.OrderedDict()
self.toolchain = None
self.verbose = False
self.cmds = []
self.pcf = None
self.sdc = None
self.xdc = None
self.params_file = None
self.params_string = None
self._strategy = None
self._carry = None
self.seed = None
self.build = None
self.build_type = None
self.date = datetime.datetime.utcnow()
self.family = None
self.device = None
self.package = None
self.part = None
self.board = None
self.project_name = None
self.srcs = None
self.top = None
self.out_dir = None
self.clocks = None
with Timed(self, 'nop'):
subprocess.check_call("true", shell=True, cwd=self.out_dir)
def run(self, pnr, args):
with Timed(self, 'total'):
os.makedirs(self.out_dir, exist_ok=True)
for f in self.srcs:
self.files.append({
'name': os.path.realpath(f),
'file_type': 'verilogSource'
})
if self.pcf is not None:
self.files.append({
'name': os.path.realpath(self.pcf),
'file_type': 'PCF'
})
self.edam = {
'files': self.files,
'name': self.project_name,
'toplevel': self.top,
'tool_options': {
'icestorm': {
'nextpnr_options': args.split(),
'arachne_pnr_options': args.split(),
'pnr': pnr,
'part': self.device
}
}
}
self.backend = edalize.get_edatool('icestorm')(
edam=self.edam, work_root=self.out_dir)
self.backend.configure("")
self.backend.build()
self.backend.build_main('timing')
def cmd(self, cmd, argstr, env=None):
print("Running: %s %s" % (cmd, argstr))
self.cmds.append('%s %s' % (cmd, argstr))
# Use this to checkpoint various stages
# If a command fails, we'll have everything up to it
self.write_metadata(all=False)
cmd_base = os.path.basename(cmd)
with open("%s/%s.txt" % (self.out_dir, cmd_base), "w") as f:
f.write("Running: %s %s\n\n" % (cmd_base, argstr))
with Timed(self, cmd_base):
if self.verbose:
cmdstr = "(%s %s) |&tee -a %s.txt; (exit $PIPESTATUS )" % (
cmd, argstr, cmd
)
print("Running: %s" % cmdstr)
print(" cwd: %s" % self.out_dir)
else:
cmdstr = "(%s %s) >& %s.txt" % (cmd, argstr, cmd_base)
subprocess.check_call(
cmdstr,
shell=True,
executable='bash',
cwd=self.out_dir,
env=env
)
def run(self):
with Timed(self, 'bit-all'):
print('top: %s' % self.top)
env = os.environ.copy()
env["SRCS"] = ' '.join(self.srcs)
env["TOP"] = self.top
env["ICECUBEDIR"] = self.icecubedir
#env["ICEDEV"] = 'hx8k-ct256'
env["ICEDEV"] = self.device + '-' + self.package
args = "--syn %s" % (self.syn(), )
if self.strategy:
args += " --strategy %s" % (self.strategy, )
self.cmd(root_dir + "/icecubed.sh", args, env=env)
self.cmd("iceunpack", "my.bin my.asc")
self.cmd("icetime", "-tmd %s my.asc" % (self.device, ))
def run_steps(self):
with Timed(self, 'synthesis'):
self.backend.build_main(self.top + '.eblif')
with Timed(self, 'pack'):
self.backend.build_main(self.top + '.net')
with Timed(self, 'place'):
self.backend.build_main(self.top + '.place')
with Timed(self, 'route'):
self.backend.build_main(self.top + '.route')
with Timed(self, 'fasm'):
self.backend.build_main(self.top + '.fasm')
with Timed(self, 'bitstream'):
self.backend.build_main(self.top + '.bit')
def run(self):
# acceptable for either device
assert (self.device, self.package) in [('up3k', 'uwg30'),
('up5k', 'uwg30'),
('up5k', 'sg48')]
with Timed(self, 'bit-all'):
env = os.environ.copy()
env["SRCS"] = ' '.join(self.srcs)
env["TOP"] = self.top
env["RADIANTDIR"] = self.radiantdir
env["RADDEV"] = self.device + '-' + self.package
syn = self.syn()
args = "--syn %s" % (syn, )
if self.strategy:
args += " --strategy %s" % self.strategy
self.cmd(root_dir + "/radiant.sh", args, env=env)
self.cmd("iceunpack", "my.bin my.asc")
self.cmd("icetime", "-tmd up5k my.asc")
def train(args):
# initalize dataset
with Timed('Loading dataset'):
ds = tiny_words(max_text_length=hp.max_text_length,
max_audio_length=hp.max_audio_length,
max_dataset_size=args.data_size)
# initialize model
with Timed('Initializing model.'):
encoder = Encoder(ds.lang.num_chars,
hp.embedding_dim,
hp.encoder_bank_k,
hp.encoder_bank_ck,
hp.encoder_proj_dims,
hp.encoder_highway_layers,
hp.encoder_highway_units,
hp.encoder_gru_units,
dropout=hp.dropout,
use_cuda=hp.use_cuda)
decoder = AttnDecoder(hp.max_text_length,
hp.attn_gru_hidden_size,
hp.n_mels,
hp.rf,
hp.decoder_gru_hidden_size,
hp.decoder_gru_layers,
dropout=hp.dropout,
use_cuda=hp.use_cuda)
postnet = PostNet(hp.n_mels,
1 + hp.n_fft // 2,
hp.post_bank_k,
hp.post_bank_ck,
hp.post_proj_dims,
hp.post_highway_layers,
hp.post_highway_units,
hp.post_gru_units,
use_cuda=hp.use_cuda)
if args.multi_gpus:
all_devices = list(range(torch.cuda.device_count()))
encoder = nn.DataParallel(encoder, device_ids=all_devices)
decoder = nn.DataParallel(decoder, device_ids=all_devices)
postnet = nn.DataParallel(postnet, device_ids=all_devices)
if hp.use_cuda:
encoder.cuda()
decoder.cuda()
postnet.cuda()
# initialize optimizers and criterion
all_paramters = (list(encoder.parameters()) +
list(decoder.parameters()) +
list(postnet.parameters()))
optimizer = optim.Adam(all_paramters, lr=hp.lr)
criterion = nn.L1Loss()
# configuring traingin
print_every = 100
save_every = 1000
# Keep track of time elapsed and running averages
start = time.time()
print_loss_total = 0 # Reset every print_every
for epoch in range(1, hp.n_epochs + 1):
# get training data for this cycle
mels, mags, indexed_texts = ds.next_batch(hp.batch_size)
mels_v = Variable(torch.from_numpy(mels).float())
mags_v = Variable(torch.from_numpy(mags).float())
texts_v = Variable(torch.from_numpy(indexed_texts))
if hp.use_cuda:
mels_v = mels_v.cuda()
mags_v = mags_v.cuda()
texts_v = texts_v.cuda()
loss = train_batch(mels_v,
mags_v,
texts_v,
encoder,
decoder,
postnet,
optimizer,
criterion,
multi_gpus=args.multi_gpus)
# Keep track of loss
print_loss_total += loss
if epoch == 0:
continue
if epoch % print_every == 0:
print_loss_avg = print_loss_total / print_every
print_loss_total = 0
print_summary = '%s (%d %d%%) %.4f' % \
(time_since(start, epoch / hp.n_epochs),
epoch, epoch / hp.n_epochs * 100, print_loss_avg)
print(print_summary)
if epoch % save_every == 0:
save_checkpoint({
'epoch': epoch + 1,
'encoder': encoder.state_dict(),
'decoder': decoder.state_dict(),
'postnet': postnet.state_dict(),
'optimizer': optimizer.state_dict(),
})
def run_steps(self):
with Timed(self, 'bitstream'):
self.backend.build_main(self.project_name + '.bit')
with Timed(self, 'fasm2bels'):
self.backend.build_main('timing_summary.rpt')
def run(self):
with Timed(self, 'total'):
with Timed(self, 'prepare'):
os.makedirs(self.out_dir, exist_ok=True)
for f in self.srcs:
self.files.append({
'name': os.path.realpath(f),
'file_type': 'verilogSource'
})
if self.xdc:
self.files.append({
'name': os.path.realpath(self.xdc),
'file_type': 'xdc'
})
if self.pcf:
self.files.append({
'name': os.path.realpath(self.pcf),
'file_type': 'PCF'
})
chip = self.family + self.device
chipdb = os.path.join(
self.rootdir, 'env', 'conda', 'pkgs', 'nextpnr-xilinx*',
'share', 'nextpnr-xilinx',
'{}{}.bin'.format(self.family, self.part))
self.files.append({
'name': os.path.realpath(chipdb),
'file_type': 'bba'
})
if self.fasm2bels:
symbiflow = os.getenv('SYMBIFLOW', None)
assert symbiflow
device_aliases = {"a35t": "a50t"}
chip_replace = chip
for k, v in device_aliases.items():
chip_replace = chip.replace(k, v)
device_path = os.path.join(symbiflow, 'share', 'symbiflow',
'arch',
'{}_test'.format(chip_replace))
self.files.append({
'name':
os.path.realpath(
os.path.join(device_path, '*rr_graph.real.bin')),
'file_type':
'RRGraph'
})
self.files.append({
'name':
os.path.realpath(
os.path.join(device_path, 'vpr_grid_map.csv')),
'file_type':
'VPRGrid'
})
self.edam = {
'files': self.files,
'name': self.project_name,
'toplevel': self.top,
'tool_options': {
'symbiflow': {
'part':
chip,
'package':
self.package,
'vendor':
'xilinx',
'builddir':
'.',
'pnr':
'nextpnr',
'yosys_synth_options':
["-flatten", "-nowidelut", "-abc9", "-arch xc7"],
'fasm2bels':
self.fasm2bels,
'dbroot':
self.dbroot,
'clocks':
self.clocks,
}
}
}
self.backend = edalize.get_edatool('symbiflow')(
edam=self.edam, work_root=self.out_dir)
self.backend.configure("")
self.backend.build_main(self.project_name + '.fasm')
self.run_steps()
self.add_runtimes()
def run_steps(self):
with Timed(self, 'bitstream'):
self.backend.build_main(self.project_name + '.bit')
def run(self):
with Timed(self, 'total'):
with Timed(self, 'prepare'):
os.makedirs(self.out_dir, exist_ok=True)
for f in self.srcs:
self.files.append({
'name': os.path.realpath(f),
'file_type': 'verilogSource'
})
if self.pcf:
self.files.append({
'name': os.path.realpath(self.pcf),
'file_type': 'PCF'
})
if self.sdc:
self.files.append({
'name': os.path.realpath(self.sdc),
'file_type': 'SDC'
})
if self.xdc:
self.files.append({
'name': os.path.realpath(self.xdc),
'file_type': 'xdc'
})
chip = self.family + self.device
tool_params = self.get_tool_params()
if self.fasm2bels:
symbiflow = os.getenv('SYMBIFLOW', None)
assert symbiflow
device_aliases = {"a35t": "a50t"}
chip_replace = chip
for k, v in device_aliases.items():
chip_replace = chip.replace(k, v)
device_path = os.path.join(symbiflow, 'share', 'symbiflow',
'arch',
'{}_test'.format(chip_replace))
self.files.append({
'name':
os.path.realpath(
os.path.join(device_path, '*rr_graph.real.bin')),
'file_type':
'RRGraph'
})
self.files.append({
'name':
os.path.realpath(
os.path.join(device_path, 'vpr_grid_map.csv')),
'file_type':
'VPRGrid'
})
self.edam = {
'files': self.files,
'name': self.project_name,
'toplevel': self.top,
'tool_options': {
'symbiflow': {
'part': chip,
'package': self.package,
'vendor': 'xilinx',
'builddir': '.',
'pnr': 'vpr',
'options': tool_params,
'fasm2bels': self.fasm2bels,
'dbroot': self.dbroot,
'clocks': self.clocks,
}
}
}
self.backend = edalize.get_edatool('symbiflow')(
edam=self.edam, work_root=self.out_dir)
self.backend.configure("")
self.run_steps()
def run(self):
with Timed(self, 'total'):
with Timed(self, 'prepare'):
os.makedirs(self.out_dir, exist_ok=True)
for f in self.srcs:
self.files.append(
{
'name': os.path.realpath(f),
'file_type': 'verilogSource'
}
)
assert self.xdc
self.files.append(
{
'name': os.path.realpath(self.xdc),
'file_type': 'xdc'
}
)
chip = self.family + self.device
out = subprocess.run(
["find", ".", "-name", "nextpnr-xilinx"],
stdout=subprocess.PIPE
)
nextpnr_locations = out.stdout.decode('utf-8').split('\n')
for location in nextpnr_locations:
if "/bin/nextpnr-xilinx" in location:
nextpnr_location = os.path.abspath(
os.path.dirname(location)
)
break
assert nextpnr_location
share_dir = os.path.join(nextpnr_location, '..', 'share')
chipdb = os.path.join(
share_dir, 'nextpnr-xilinx',
'{}{}.bin'.format(self.family, self.part)
)
self.files.append(
{
'name': os.path.realpath(chipdb),
'file_type': 'bba'
}
)
if self.fasm2bels:
symbiflow = os.getenv('SYMBIFLOW', None)
assert symbiflow
device_aliases = {"a35t": "a50t"}
chip_replace = chip
for k, v in device_aliases.items():
chip_replace = chip.replace(k, v)
device_path = os.path.join(
symbiflow, 'share', 'symbiflow', 'arch',
'{}_test'.format(chip_replace)
)
self.files.append(
{
'name':
os.path.realpath(
os.path.join(
device_path, '*rr_graph.real.bin'
)
),
'file_type':
'RRGraph'
}
)
self.files.append(
{
'name':
os.path.realpath(
os.path.join(
device_path, 'vpr_grid_map.csv'
)
),
'file_type':
'VPRGrid'
}
)
symbiflow_options = {
'part':
chip,
'package':
self.package,
'vendor':
'xilinx',
'builddir':
'.',
'pnr':
'nextpnr',
'yosys_synth_options':
[
"-flatten", "-nowidelut", "-abc9", "-arch xc7",
"-nocarry", "-nodsp"
],
'fasm2bels':
self.fasm2bels,
'dbroot':
self.dbroot,
'clocks':
self.clocks,
'environment_script':
os.path.abspath('env.sh') + ' nextpnr xilinx-' +
self.device,
'options':
'--timing-allow-fail'
}
if self.fasm2bels:
bitstream_device = None
if self.device.startswith('a'):
bitstream_device = 'artix7'
if self.device.startswith('z'):
bitstream_device = 'zynq7'
if self.device.startswith('k'):
bitstream_device = 'kintex7'
assert bitstream_device
part_json = os.path.join(
self.dbroot, bitstream_device, self.family + self.part,
'part.json'
)
symbiflow_options['yosys_additional_commands'] = [
"plugin -i xdc",
"yosys -import",
"read_xdc -part_json {} {}".format(
part_json, os.path.realpath(self.xdc)
),
"clean",
"write_blif -attr -param {}.eblif".format(
self.project_name
),
]
self.edam = {
'files': self.files,
'name': self.project_name,
'toplevel': self.top,
'tool_options': {
'symbiflow': symbiflow_options,
}
}
self.backend = edalize.get_edatool('symbiflow')(
edam=self.edam, work_root=self.out_dir
)
self.backend.configure("")
self.backend.build_main(self.project_name + '.fasm')
self.run_steps()
self.add_runtimes()
self.add_wirelength()
def run(self):
with Timed(self, 'total'):
with Timed(self, 'prepare'):
os.makedirs(self.out_dir, exist_ok=True)
for f in self.srcs:
self.files.append(
{
'name': os.path.realpath(f),
'file_type': 'verilogSource'
}
)
if self.pcf:
self.files.append(
{
'name': os.path.realpath(self.pcf),
'file_type': 'PCF'
}
)
if self.sdc:
self.files.append(
{
'name': os.path.realpath(self.sdc),
'file_type': 'SDC'
}
)
if self.xdc:
self.files.append(
{
'name': os.path.realpath(self.xdc),
'file_type': 'xdc'
}
)
chip = self.family + self.device
tool_params = []
symbiflow_options = {
'part':
self.device,
'package':
self.package,
'vendor':
'quicklogic',
'builddir':
'.',
'pnr':
'vpr',
'options':
tool_params,
'fasm2bels':
self.fasm2bels,
'dbroot':
self.dbroot,
'clocks':
self.clocks,
'seed':
self.seed,
'environment_script':
os.path.abspath('env.sh') + ' quicklogic',
}
self.edam = {
'files': self.files,
'name': self.project_name,
'toplevel': self.top,
'tool_options': {
'symbiflow': symbiflow_options
}
}
self.backend = edalize.get_edatool('symbiflow')(
edam=self.edam, work_root=self.out_dir
)
self.backend.configure("")
self.run_steps()