def build_phase(self, phase): super().build_phase(phase) self.sqr = ram_sequencer.type_id.create("sqr", self) self.drv = ram_driver.type_id.create("drv", self) self.mon = ram_monitor.type_id.create("mon", self) arr = [] if UVMConfigDb.get(self, "", "vif", arr): self.vif = arr[0] if self.vif is None: uvm_fatal("RAM/AGT/NOVIF", "No virtual interface speficied") UVMConfigDb.set(self, "", "master_id", self.master_id)
def __init__(self, name, parent=None, T=packet): UVMComponent.__init__(self, name, parent) self.out = UVMBlockingPutPort("out", self) self.num_packets = 10 nn = [] self.T = T self.add_objection = True self.proto = self.T("my_packet") if UVMConfigDb.get(self, "", "num_packets", nn): self.num_packets = nn[0]
def build_phase(self, phase): self.sqr = apb_sequencer.type_id.create("sqr", self) self.drv = apb_master.type_id.create("drv", self) self.mon = apb_monitor.type_id.create("mon", self) arr = [] if UVMConfigDb.get(self, "", "vif", arr): self.vif = arr[0] if self.vif is None: uvm_fatal("APB/AGT/NOVIF", "No virtual interface specified for apb_agent instance")
async def body(self): arr = [] if UVMConfigDb.get(None, "", "dut", arr): self.dut = arr[0] else: uvm_fatal("NO_DUT", "Could not find DUT from config_db") model = self.model dma_ram = model.DMA_RAM bkd = mem_backdoor("backdoor") dma_ram.set_backdoor(bkd) bkd.dut = self.dut for i in range(10): status = [] data = 0x1234 offset = i * 4 await dma_ram.write(status, offset, data) await Timer(100, "NS") status = [] data = [] offset = i * 4 await dma_ram.read(status, offset, data) exp = data[0] await Timer(100, "NS") status = [] data = [] await dma_ram.read(status, offset, data, path=UVM_BACKDOOR) if exp != data[0]: uvm_error("MEM_READ_ERR", "Exp: {}, Got: {}".format(exp, data[0])) # Test backdoor access with write/read operation ref_data = 0xBEEFFACE status = [] await Timer(100, "NS") await dma_ram.write(status, offset, ref_data, path=UVM_BACKDOOR) status = [] data = [] await Timer(100, "NS") await dma_ram.read(status, offset, data, path=UVM_BACKDOOR) if data[0] != ref_data: uvm_fatal("MEM_DATA_ERR", "Exp: {}, Got: {}".format(ref_data, data[0])) await Timer(100, "NS")
def build_phase(self, phase): if self.regmodel is None: self.regmodel = dut_regmodel.type_id.create( "regmodel", None, self.get_full_name()) self.regmodel.build() self.regmodel.lock_model() self.apb = apb_agent.type_id.create("apb", self) if EXPLICIT_MON: self.apb2reg_predictor = UVMRegPredictor("apb2reg_predictor", self) hdl_root = "dut" sv.value_plusargs("ROOT_HDL_PATH=%s", hdl_root) # cast to 'void' removed self.regmodel.set_hdl_path_root(hdl_root) vif = [] if UVMConfigDb.get(self, "apb", "vif", vif): self.vif = vif[0] else: uvm_fatal("NO_VIF", "Could not find vif from config DB")
def build_phase(self, phase): vif = [] if not (UVMConfigDb.get(self, "", "vif", vif)): uvm_fatal("NOVIF", ("virtual interface must be set for: " + self.get_full_name() + ".vif")) self.vif = vif[0]
def build_phase(self, phase): UVMTest.build_phase(self, phase) self.env = tb_env.type_id.create("env", self) UVMConfigDb.set(self.env, "bus", "dut", self.dut)