async def body(self):
uvm_info(self.get_type_name(),
sv.sformatf("%s starting...", self.get_sequence_path()),
UVM_MEDIUM)
# READ A RANDOM LOCATION
self.read_byte_seq0 = read_byte_seq("read_byte_seq")
await uvm_do_with(self, self.read_byte_seq0, {})
self.addr_check = self.read_byte_seq0.rsp.addr
self.m_data0_check = self.read_byte_seq0.rsp.data[0] + 1
# WRITE MODIFIED READ DATA
self.write_byte_seq0 = write_byte_seq("write_byte_seq")
self.write_byte_seq0.start_addr = self.addr_check
self.write_byte_seq0.data0 = self.m_data0_check
await uvm_do_with(self, self.write_byte_seq0, {})
# { write_byte_seq0.start_addr == addr_check;
# write_byte_seq0.data0 == m_data0_check; } )
self.m_data0_check = write_byte_seq.last_data
# // READ MODIFIED WRITE DATA
self.read_byte_seq0.start_addr = self.addr_check
await uvm_do_with(self, self.read_byte_seq0,
lambda start_addr: start_addr == self.addr_check)
data0_got = int(self.read_byte_seq0.rsp.data[0])
if self.m_data0_check != data0_got:
uvm_error(
self.get_type_name(),
sv.sformatf(
"%s Read Modify Write Read error!\n\tADDR: %h, EXP: %h, ACT: %h",
self.get_sequence_path(), self.addr_check,
self.m_data0_check, data0_got))
else:
self.test_pass = True
def do_compare(self, rhs, comparer):
rhs_ = []
if not sv.cast(rhs_,rhs, UVMBuiltInPair):
uvm_error("WRONG_TYPE", {"do_compare: rhs argument is not of type '",
self.get_type_name(),"'"})
return 0
rhs_ = rhs[0]
return self.first == rhs_.first and self.second == rhs_.second
def configure(self, blk_parent, regfile_parent, hdl_path=""):
if blk_parent is None:
uvm_error("UVM/RFILE/CFG/NOBLK", (
"UVMRegFile::configure() called without a parent block for instance '"
+ self.get_name() + "' of register file type '",
self.get_type_name() + "'."))
return
self.parent = blk_parent
self.m_rf = regfile_parent
self.add_hdl_path(hdl_path)
async def run_phase(self, phase):
self.comp.set_config_int_test = True
phase.raise_objection(self)
await Timer(100, 'ns')
for i in range(10):
if i < 9:
uvm_error("TestMaxQuitCountInfo", "Error " + str(i))
else:
# Need to catch this because max_quit_count reached
try:
uvm_error("TestMaxQuitCountInfo", "Last Error " + str(i))
except Exception as e:
uvm_info("TestMaxQuitCount_CAUGHT", "Exception: " + str(e),
UVM_NONE)
self.caught = True
await Timer(100, 'ns')
phase.drop_objection(self)
async def test_test(dut):
ep = UVMEventPool("ep")
cs_ = UVMCoreService.get()
e = None
e = ep.get("fred")
e = ep.get("george")
e_data = ep.get('evt_data')
uvm_default_table_printer.knobs.reference = 0
ep.print_obj()
trig_proc = cocotb.fork(trig_event(e))
cocotb.fork(trig_data_event(e_data))
await e_data.wait_trigger()
await e.wait_on()
e.reset()
await Timer(1, "NS")
trig_proc = cocotb.fork(trig_event(e))
evt_proc = cocotb.fork(wait_on_evt(e))
await sv.fork_join([trig_proc, evt_proc])
svr = None # uvm_report_server
svr = cs_.get_report_server()
svr.report_summarize()
time_ok = sv.realtime("NS") == 202
data_ok = e_data.get_trigger_data() == 0x1234
if data_ok and time_ok and (svr.get_severity_count(UVM_FATAL) +
svr.get_severity_count(UVM_ERROR) == 0):
print("** UVM TEST PASSED **\n")
else:
if data_ok is False:
uvm_error(
"DATA_ERROR",
"Exp: {}, Got: {}".format(0x1234, e_data.get_trigger_data()))
if time_ok is False:
uvm_error("TIME_ERROR",
"Exp: {}, Got: {}".format(202, sv.realtime("NS")))
raise Exception("!! UVM TEST FAILED !!\n")
def configure(self, blk_parent, regfile_parent, hdl_path=""):
"""
Function: configure
Configure a register file instance
Specify the parent block and register file of the register file
instance.
If the register file is instantiated in a block,
`regfile_parent` is specified as `None`.
If the register file is instantiated in a register file,
`blk_parent` must be the block parent of that register file and
`regfile_parent` is specified as that register file.
If the register file corresponds to a hierarchical RTL structure,
its contribution to the HDL path is specified as the `hdl_path`.
Otherwise, the register file does not correspond to a hierarchical RTL
structure (e.g. it is physically flattened) and does not contribute
to the hierarchical HDL path of any contained registers.
extern function void configure (uvm_reg_block blk_parent,
uvm_reg_file regfile_parent,
string hdl_path = "")
Args:
blk_parent:
regfile_parent:
hdl_path:
"""
if blk_parent is None:
uvm_error("UVM/RFILE/CFG/NOBLK", (
"UVMRegFile::configure() called without a parent block for instance '"
+ self.get_name() + "' of register file type '",
self.get_type_name() + "'."))
return
self.parent = blk_parent
self.m_rf = regfile_parent
self.add_hdl_path(hdl_path)