def check_phase(self, phase):
self.check_phase_ran = True
if self.caught is False:
uvm_fatal("TestMaxQuitCount TEST FAILED",
"Did not catch the exception correctly")
if self.comp.tag != 'matched_correctly':
uvm_fatal("TestMaxQuitCount TEST FAILED",
"+uvm_set_config_string did not match correctly")
def build_phase(self, phase):
# Need to be called, in order to trigger auto-config
super().build_phase(phase)
if self.uvm_report_enabled(UVM_DEBUG):
uvm_fatal("MyComponent", "Verbosity UVM_DEBUG must not be enabled")
if not self.uvm_report_enabled(UVM_HIGH):
uvm_fatal("MyComponent", "Verbosity not UVM_HIGH in build_Phase")
self.verb_checked_build_phase = True
async def reset_dut(self):
env = self.get_child("env")
if env is None:
uvm_fatal("test", "Cannot find tb_env")
uvm_info("Test", "Resetting DUT...", UVM_LOW)
self.dut.reset <= 0
await Timer(5, "NS")
self.dut.reset <= 1
env.regmodel.reset()
def build_phase(self, phase):
UVMTest.build_phase(self, phase)
# Enable transaction recording for everything
UVMConfigDb.set(self, "*", "recording_detail", UVM_FULL)
# Create the tb
self.ubus_example_tb0 = ubus_example_tb.type_id.create("ubus_example_tb0", self)
# Create a specific depth printer for printing the created topology
self.printer = UVMTablePrinter()
self.printer.knobs.depth = 3
arr = []
if UVMConfigDb.get(None, "*", "vif", arr) is True:
UVMConfigDb.set(self, "*", "vif", arr[0])
else:
uvm_fatal("NOVIF", "Could not get vif from config DB")
async def wait_for_change(self, element): # task
"""
Task: wait_for_change
Wait for a change in the value of the register or memory
element in the DUT.
When self method returns, the mirror value for the register
corresponding to self instance of the backdoor class will be updated
via a backdoor read operation.
Args:
element:
"""
uvm_fatal("RegModel", "UVMRegBackdoor::wait_for_change() method has not been overloaded")
async def write(self, rw): # task
"""
Task: write
User-defined backdoor write operation.
Call <do_pre_write()>.
Deposit the specified value in the specified register HDL implementation.
Call <do_post_write()>.
Returns an indication of the success of the operation.
extern def write(self,uvm_reg_item rw)
Args:
rw:
"""
uvm_fatal("RegModel", "UVMRegBackdoor::write() method has not been overloaded")
def read_func(self, rw):
"""
Function: read_func
User-defined backdoor read operation.
Peek the current value in the HDL implementation.
Returns the current value and an indication of the success of
the operation.
extern virtual def void read_func(self,uvm_reg_item rw):
Args:
rw:
"""
uvm_fatal("RegModel", "UVMRegBackdoor::read_func() method has not been overloaded")
rw.status = UVM_NOT_OK
async def run_phase(self, phase):
phase.raise_objection(self)
env = self.get_child("env")
if env is None:
uvm_fatal("test", "Cannot find tb_env")
await self.reset_dut()
#env.regmodel.reset()
clk_fork = cocotb.fork(MyClock(self.dut).start(2000))
#uvm_reg_sequence seq;
seq = UVMRegHWResetSeq.type_id.create("reg_hw_rst_seq")
seq.model = env.regmodel
print("Before seq.start. Wait for seq state")
await seq.start(None)
print("seq.start was called. Wait for seq state")
await seq.wait_for_sequence_state(UVM_FINISHED)
print("AFTER yield seq.wait_for_sequence_state(UVM_FINISHED)")
nwrites = 8
uvm_info("Test", "Performing " + str(nwrites) + " writes...", UVM_LOW)
for i in range(nwrites):
status = []
uvm_info("WRITE", sv.sformatf("Write[%0d] now", i), UVM_LOW)
await env.regmodel.user_acp.write(status, sv.random())
if status[0] == UVM_NOT_OK:
raise Exception("Reg_write " + i + " failed with UVM_NOT_OK")
else:
uvm_info("WRITE_DONE", "UVM_OK status returned for write " +
str(i), UVM_LOW)
status = []
print("Now mirroring the reg status..")
await env.regmodel.user_acp.mirror(status, UVM_CHECK)
await self.reset_dut()
status = []
print("Now mirroring the reg status after reset")
await env.regmodel.user_acp.mirror(status, UVM_CHECK)
await Timer(100, "NS")
clk_fork.kill()
phase.drop_objection(self)
def check_phase(self, phase):
uvm_fatal("FAT2WARN", "Severity should change UVM_FATAL->UVM_WARN")
if self.set_config_int_test:
if self.hex_to_match != 0x789:
uvm_fatal("HEX_NUM_CONFIG_INT_FATAL",
"hex_to_match not auto-configured correctly")
if self.oct_to_match != int('456', 8):
uvm_fatal("OCT_NUM_CONFIG_INT_FATAL",
"oct_to_match not auto-configured correctly")
if self.dec_to_match < 1000000000:
uvm_fatal("DEC_NUM_CONFIG_INT_FATAL",
"dec_to_match not auto-configured correctly")
async def run_phase(self, phase):
self.uvm_report_info("component", "before raising objection", UVM_MEDIUM)
phase.raise_objection(self)
if self.uvm_report_enabled(UVM_DEBUG):
uvm_fatal("MyComponent", "Verbosity UVM_DEBUG must not be enabled")
#UVMDebug.DEBUG = False
self.uvm_report_info("component", "after raising objection", UVM_MEDIUM)
await Timer(1, 'ns')
uvm_debug(self, 'run_phase', "Objection raised run_phase " +
self.get_name())
await Timer(2, 'ns')
self.uvm_report_info("component", "hello out there!", UVM_MEDIUM)
await Timer(1005, 'ns')
assert(self.m_rh is self.old_rh)
self.uvm_report_info("component", "hello after 1005ns!", UVM_HIGH)
# verb_level = self.get_report_verbosity_level()
if not self.uvm_report_enabled(UVM_DEBUG):
uvm_fatal("MyComponent", "Verbosity UVM_DEBUG must be enabled after 1000ns")
self.uvm_report_info("component", "finishing up!", UVM_MEDIUM)
self.uvm_report_fatal("SUPPRESS_FATAL",
"Should not give FATAL due to cmdline arg +uvm_set_action")
phase.drop_objection(self)
def __init__(self, name="DummyTest", parent=None):
super().__init__(name, parent)
uvm_fatal("DUMM_TEST", "Tests fails if this test is created")
def check_phase(self, phase):
if not self.env.all_ok():
uvm_fatal("ENV_NOT_OK", "There were errors in the env")
async def pre_configure_phase(self, phase):
t = []
if (UVMConfigDb.get(self, "pre_configure", "timeout", t) and t[0] > 0):
await Timer(t[0], "NS")
uvm_fatal("TIMEOUT", "Time-out expired in pre_configure phase")
def report_phase(self, phase):
if self.test_pass:
uvm_info(self.get_type_name(), "** UVM TEST PASSED **", UVM_NONE)
else:
uvm_fatal(self.get_type_name(),
"** UVM TEST FAIL **\n" + self.err_msg)
def wait_for_change(self, element): # task
uvm_fatal("RegModel", "UVMRegBackdoor::wait_for_change() method has not been overloaded")
def read_func(self, rw):
uvm_fatal("RegModel", "UVMRegBackdoor::read_func() method has not been overloaded")
rw.status = UVM_NOT_OK
def write(self, rw): # task
uvm_fatal("RegModel", "UVMRegBackdoor::write() method has not been overloaded")
def shutdown_phase(self, phase):
t = []
if (UVMConfigDb.get(self, "shutdown", "timeout", t) and t[0] > 0):
yield Timer(t[0], "NS")
uvm_fatal("TIMEOUT", "Time-out expired in shutdown phase")
async def reset_phase(self, phase):
t = []
if (UVMConfigDb.get(self, "reset", "timeout", t) and t[0] > 0):
await Timer(t[0], "NS")
uvm_fatal("TIMEOUT", "Time-out expired in reset phase")
def post_reset_phase(self, phase):
t = []
if (UVMConfigDb.get(self, "post_reset", "timeout", t) and t[0] > 0):
yield Timer(t[0], "NS")
uvm_fatal("TIMEOUT", "Time-out expired in post_reset phase")
def configure_phase(self, phase):
t = []
if (UVMConfigDb.get(self, "configure", "timeout", t) and t[0] > 0):
yield Timer(t[0], "NS")
uvm_fatal("TIMEOUT", "Time-out expired in configure phase")
def check_phase(self, phase):
self.check_phase_ran = True
if self.comp.verb_checked_build_phase is False:
uvm_fatal("CmdLineTest", "No verb checked in my_comp")
async def post_shutdown_phase(self, phase):
t = []
if (UVMConfigDb.get(self, "post_shutdown", "timeout", t) and t[0] > 0):
await Timer(t[0], "NS")
uvm_fatal("TIMEOUT", "Time-out expired in post_shutdown phase")
