def __init__(self, Path, Prefix, Monitors, Print=False, Bwen=True):
self.Prefix = Prefix
self.Path = Path
self.Active = False
self.Print = Print
self.Bwen = Bwen
self.Ram = {}
Full = '%s.%s%s' % (self.Path, self.Prefix, 'wdata')
Full = veri.peek(Full)
self.dataWidth = len(Full)
self.strD = '%%0%dx' % (self.dataWidth / 4)
Full = '%s.%s%s' % (self.Path, self.Prefix, 'addr')
Full = veri.peek(Full)
Len = len(Full)
self.addrWidth = Len
Monitors.append(self)
if self.Bwen:
Bweb = self.peeks('bwen')
else:
Bweb = 0
logs.log_info('ramMonitor #%d setup %s dataw=%d addrw=%d bweb=%s' %
(ramMonitorClass.runnum, self.Prefix, self.dataWidth,
self.addrWidth, Bweb))
ramMonitorClass.runnum += 1
def __init__(self, Kind, Path):
self.Kind = Kind
self.Path = Path
self.Base = db.baseme(self)
self.Pins = {}
veri.force('%s.base' % (Path), str(self.Base))
if Kind == 'color':
self.Color = logs.bin2str(veri.peek('%s.color' % (Path)))
self.Clock = logs.bin2str(veri.peek('%s.clock' % (Path)))
self.refClock = logs.bin2str(veri.peek('%s.refclock' % (Path)))
if self.Clock != '':
self.Cycle = 0
self.Pins['in0'] = newNet(self, 'in0', self.Base)
self.Pins['out0'] = newNet(self, 'out0', self.Base)
elif Kind == 'blob':
self.Func = logs.bin2str(veri.peek('%s.func' % (Path)))
self.Func = self.Func.replace('||', '|')
self.Func = self.Func.replace('&&', '&')
self.Func = self.Func.replace('!', '~')
self.Vars = getVars(self.Func)
for Var in self.Vars:
self.Pins[Var] = newNet(self, Var, self.Base)
self.Pins['out0'] = newNet(self, 'out0', self.Base)
self.Vals = {}
elif Kind == 'flop':
self.Pins['clk'] = newNet(self, 'clk', self.Base)
self.Pins['dd'] = newNet(self, 'dd', self.Base)
self.Pins['qq'] = newNet(self, 'qq', self.Base)
else:
logs.log_error('kind is %s' % self.Kind)
def negedge():
global cycles, idle, Ain, state, Max
cycles += 1
veri.force('tb.cycles', str(cycles))
if (cycles > 1000):
veri.listing('tb', '1000', 'cucu.list')
veri.finish()
rst_n = veri.peek('tb.rst_n')
if (rst_n != '1'):
ain = veri.peek('tb.ain')
Len = len(ain)
Max = 1 << Len
return
veri.force('tb.en', '1')
if state == 'idle':
Ain = random.randint(0, Max)
veri.force('tb.ain', logs.make_str(Ain))
veri.force('tb.vldin', '1')
state = 'work0'
elif state == 'work0':
veri.force('tb.vldin', '0')
state = 'wait0'
elif state == 'wait0':
vldout = logs.peek('tb.vldout')
if vldout == 1:
Out = logs.peek('tb.out')
Exp = int(math.sqrt(Ain))
if Out == Exp:
logs.log_correct('in=%d out=%d' % (Ain, Out))
else:
logs.log_wrong('ain=%d max=%d expected=%d act=%d' %
(Ain, Max, int(math.sqrt(Ain)), Out))
state = 'idle'
def cucu():
veri.force('tb.paddr', '0')
veri.force('tb.psel', '0')
veri.force('tb.psize', '0')
veri.force('tb.pwdata', '0')
veri.force('tb.pwrite', '0')
outmix = intx(veri.peek('tb.outmix'))
prdata = intx(veri.peek('tb.prdata'))
def cucu():
veri.force('tb.ram_rdata', '0')
veri.force('tb.resetn', '0')
veri.force('tb.rxd', '0')
ram_addr = intx(veri.peek('tb.ram_addr'))
ram_read = intx(veri.peek('tb.ram_read'))
ram_wdata = intx(veri.peek('tb.ram_wdata'))
ram_write = intx(veri.peek('tb.ram_write'))
txd = intx(veri.peek('tb.txd'))
def loopback():
if veri.peek('tb.rx_valid1') == '1':
veri.force('tb.read_rx1', '1')
fdata = veri.peek('tb.rxdata1')
veri.force('tb.txdata1', '0b' + fdata)
veri.force('tb.write_tx1', '1')
else:
veri.force('tb.write_tx1', '0')
veri.force('tb.read_rx1', '0')
def run(self, Area):
if self.state == 'read':
md_rvalid = veri.peek('%s.md_rvalid' % self.Path)
if md_rvalid == '1':
md_rdata = logs.peek('%s.md_rdata' % self.Path)
md_rresp = logs.peek('%s.md_rresp' % self.Path)
md_rid = logs.peek('%s.md_rid' % self.Path)
logs.log_info(
'read addr=0x%x data=0x%x %x %x %s %s' %
(self.Addr, md_rdata, md_rresp, md_rid, Area, self.Note))
self.state = 'idle'
self.waiting = 100
if self.waiting > 0:
self.waiting -= 1
if (self.waiting < 5) and (self.state == 'read'):
logs.log_info('read addr=%0x%x didnt end' % (self.Addr))
self.state = 'idle'
return
ext_core_rst_n = veri.peek('%s.ext_core_rst_n' % self.Path)
veri.force('%s.tl42x_ocem_core_rst_r' % self.Path, ext_core_rst_n)
if ext_core_rst_n == '0': return
if self.state == 'idle':
if self.wrqueue == []: return
self.Kind, self.Addr, self.Data, self.Note = self.wrqueue.pop(0)
self.state = 'addr'
return
if self.state == 'addr':
Ok = self.driveAddr(self.Addr, True)
if Ok: self.state = 'addr1'
elif self.state == 'addr1':
self.driveAddr(self.Addr, False)
self.waiting = 2
if self.Kind == 'write':
self.state = 'data'
else:
self.state = 'read'
self.waiting = 100
elif self.state == 'data':
Ok = self.driveData(self.Data, True)
if Ok: self.state = 'after'
elif self.state == 'after':
self.driveData(self.Data, False)
if self.Area:
Area = self.Area
logs.log_info('written addr=0x%x data=0x%x %s %s' %
(self.Addr, self.Data, Area, self.Note))
self.state = 'window'
self.waiting = 100
elif self.state == 'window':
self.state = 'idle'
def check_pattern(self):
Exit = ''
Failed = False
for Ind in range(0, self.ithlen):
Char = self.pattern[Ind]
Sig = self.swavpos[Ind]
Exit = Exit + Char
if (Char == '?'):
Now = veri.peek('tb.' + Sig)
Exit = Exit[0:-1] + look(NN)
elif (Char in ['H', 'L']) and (Sig != 'sda'):
Now = veri.peek('tb.' + Sig)
if ((not (Now == '0')) and (Char == 'L')):
self.bads = self.bads + 1
Failed = True
self.print_fail('fail0', Sig, Char, Now)
Exit = Exit[0:-1] + look(Now)
elif ((not (Now == '1')) and (Char == 'H')):
self.bads = self.bads + 1
Failed = True
self.print_fail('fail1', Sig, Char, Now)
Exit = Exit[0:-1] + look(Now)
elif (Now in ['X', 'Z', 'x', 'z']) and (Char in ['L', 'H']):
self.bads = self.bads + 1
Failed = True
self.print_fail('failx', Sig, Char, Now)
Exit = Exit[0:-1] + look(Now)
else:
self.goods = self.goods + 1
if (self.bads > TOOMANYBADS):
print 'too many fails'
self.Logf.close()
self.Recordf.write('pattern_end %s ;\n' % (PatternName[0]))
self.Recordf.close()
veri.finish()
else:
veri.force('tb.bads', str(self.bads))
veri.force('tb.goods', str(self.goods))
if ((self.activeline % 100) == 0):
logs.log_info(
'goods=%d bads=%d pattern_width=%d activeline=%d ' %
(self.goods, self.bads, self.ithlen, self.activeline))
if (Failed):
self.Recordf.write('V { bist = %s ; } /* %5d fail exp=%s */\n' %
(Exit, self.activeline, self.pattern))
else:
self.Recordf.write('V { bist = %s ; } /* %5d */\n' %
(Exit, self.activeline))
def negedge():
global cycles, idle, Ain, state, Max, Pause
cycles += 1
veri.force('tb.cycles', str(cycles))
if (cycles > 1000000):
veri.listing('tb', '1000', 'cucu.list')
veri.finish()
return
veri.force('tb.en', '1')
rst_n = veri.peek('tb.rst_n')
if (rst_n != '1') and (cycles < 100):
ain = veri.peek('tb.ain')
Len = len(ain)
Max = 1 << Len
veri.force('tb.makeStuckList', '1')
return
if (cycles > 30):
for Mon in Monitors:
Mon.run()
if state == 'reset':
Pause -= 1
if Pause == 0:
state = 'idle'
veri.force('tb.rst_n', '1')
elif state == 'idle':
Ain = random.randint(0, Max)
veri.force('tb.ain', logs.make_str(Ain))
veri.force('tb.vldin', '1')
state = 'work0'
elif state == 'work0':
veri.force('tb.vldin', '0')
state = 'wait0'
elif state == 'wait0':
vldout = logs.peek('tb.vldout')
if vldout == 1:
state = 'idle'
return
Out = logs.peek('tb.out')
Exp = int(math.sqrt(Ain))
if Out == Exp:
logs.log_correct('in=%d out=%d' % (Ain, Out))
else:
logs.log_wrong('ain=%d max=%d expected=%d act=%d' %
(Ain, Max, int(math.sqrt(Ain)), Out))
state = 'idle'
def run(self):
if self.waiting>0:
self.waiting -= 1
return
if self.seq!=[]:
List = self.seq.pop(0)
for (Sig,Val) in List:
if Sig=='wait':
self.waiting=int(Val)
elif Sig=='catch':
X = veri.peek('%s.%s'%(self.Path,Val))
print 'ahb read %s'%X
else:
veri.force('%s.%s'%(self.Path,Sig),str(Val))
return
if self.queue!=[]:
What = self.queue.pop(0)
if What[0]=='write':
self.seq.append([('haddr',What[1]),('hwdata',What[2]),('hwrite',1),('htrans',2),('hsize',2),('hsel',1)])
self.seq.append([('wait',1)])
self.seq.append([('haddr',0),('hwdata',0),('hwrite',0),('htrans',0),('hsize',0),('hsel',0)])
self.seq.append([('wait',5)])
if What[0]=='read':
self.seq.append([('haddr',What[1]),('hwrite',0),('htrans',2)])
self.seq.append([('wait',1)])
self.seq.append([('haddr',0),('hwrite',0),('htrans',0),('catch','hrdata')])
self.seq.append([('wait',5)])
def cucu():
veri.force('tb.paddr', '0')
veri.force('tb.psel', '0')
veri.force('tb.psize', '0')
veri.force('tb.pwdata', '0')
veri.force('tb.pwrite', '0')
enables = intx(veri.peek('tb.enables'))
gain0 = intx(veri.peek('tb.gain0'))
gain1 = intx(veri.peek('tb.gain1'))
jump0 = intx(veri.peek('tb.jump0'))
jump1 = intx(veri.peek('tb.jump1'))
jump2 = intx(veri.peek('tb.jump2'))
prdata = intx(veri.peek('tb.prdata'))
start0 = intx(veri.peek('tb.start0'))
start1 = intx(veri.peek('tb.start1'))
start2 = intx(veri.peek('tb.start2'))
def run1(self):
if veri.peek('tb.dut.dig_top.usat_tx.enable') != '1': return
cnt = logs.peek('tb.dut.dig_top.usat_tx.serializer.cnt')
if cnt != 11: return
din0 = veri.peek('tb.dut.dig_top.usat_tx.serializer.data_in_0')
din1 = veri.peek('tb.dut.dig_top.usat_tx.serializer.data_in_1')
Chr0 = encdec_8b10b.trans10to8(din0)
Chr1 = encdec_8b10b.trans10to8(din1)
Chr0 = nice(Chr0)
Chr1 = nice(Chr1)
self.Stream[0].append(Chr0)
self.Stream[1].append(Chr1)
self.dins.append(
('%03x' % (logs.intx(din1)), '%03x' % (logs.intx(din0))))
if len(self.dins) > 8: self.dins.pop(0)
if len(self.Stream[0]) > 8: self.Stream[0].pop(0)
if len(self.Stream[1]) > 8: self.Stream[1].pop(0)
# if len(self.Stream[0])==8:
# logs.log_info('STREAM side0 %d %s %s'%(len(self.Stream[0]),self.Stream[0],self.Stream[1]))
# logs.log_info('STREAM side1 %d %s %s'%(len(self.Stream[0]),self.Stream[0],self.Stream[1]))
if syncAll(self.Stream[0]) and syncAll(self.Stream[1]):
self.syncState = 'idle'
if self.syncState == 'idle':
if sync8(self.Stream[0]) and sync8(self.Stream[1]):
self.syncState = 'sync8'
self.Stream[0] = []
self.Stream[1] = []
elif self.syncState == 'sync8':
if len(self.Stream[0]) == 8:
logs.log_info('STREAM8 %s %s' %
(self.Stream[1], self.Stream[0]))
# logs.log_info('STREAM8 X %s'%str(self.dins))
self.Stream[0] = []
self.Stream[1] = []
txc_0 = logs.peek('tb.dut.dig_top.usat_tx.txc_0')
txd_0 = logs.peek('tb.dut.dig_top.usat_tx.txd_0')
txc_1 = logs.peek('tb.dut.dig_top.usat_tx.txc_1')
txd_1 = logs.peek('tb.dut.dig_top.usat_tx.txd_1')
# logs.log_info('side0 %s %s %s %02x side1 %s %s %s %02x'%(din0,Chr0,self.txc_0,self.txd_0,din1,Chr1,self.txc_1,self.txd_1))
self.txc_0 = txc_0
self.txd_0 = txd_0
self.txc_1 = txc_1
self.txd_1 = txd_1
def axi_clk():
axi.run()
if veri.peek('tb.wvalid') == '1':
wdata = logs.peek('tb.wdata')
Expecteds[-1] += int(math.sqrt(wdata))
wlast = logs.peek('tb.wlast')
if wlast == 1:
Expecteds.append(0)
def use_command_wrds(self, wrds):
if wrds == []: return
if (wrds[0] in ['quit', 'exit']):
veri.finish()
elif wrds[0] in ['slow', 'sleep']:
if len(wrds) == 1:
veri.force('tb.run_slowly', '1')
elif wrds[1] in ['True', '1']:
veri.force('tb.run_slowly', '1')
elif wrds[1] in ['False', '0']:
veri.force('tb.run_slowly', '0')
else:
print 'command "slow" or "sleep" accept one parameter: True or False or 1 or 0"'
elif wrds[0] == 'os':
Cmd = string.join(wrds[1:], ' ')
os.system(Cmd)
elif wrds[0] == 'time':
print 'time', veri.stime()
elif wrds[0] == 'eval':
Cmd = string.join(wrds[1:], ' ')
print eval(Cmd)
elif wrds[0] == 'exec':
Cmd = string.join(wrds[1:], ' ')
exec(Cmd)
elif wrds[0] in ['file', 'source']:
try:
Fin = open(wrds[1])
except:
print 'failed to open %s' % wrds[1]
return
lines = Fin.readlines()
Fin.close()
for line in lines:
wrds0 = string.split(line)
print '>>', wrds0
use_command_wrds(self, wrds0)
elif (wrds[0] == 'clear'):
apb.wrqueue = []
elif (wrds[0] == 'history'):
for ind, X in enumerate(CommandsHistory):
print ind, X
elif (wrds[0] == 'reset'):
veri.force('tb.rst_n', '0')
apb.waiting = 20
elif (wrds[0] == 'listing'):
veri.listing('tb', '100', 'deep.list')
elif (wrds[0] == 'force'):
veri.force(wrds[1], wrds[2])
elif (wrds[0] == 'peek'):
Val = veri.peek(wrds[1])
logs.log_info('peeking %s 0x%x %s' %
(wrds[1], logs.intx(Val), Val))
elif (wrds[0] == 'apb'):
Addr = eval(wrds[1])
Data = eval(wrds[2])
apb.wrqueue.append((Addr, Data))
else:
print 'y ', HELP
def negedge():
global cycles
cycles += 1
veri.force('tb.cycles', str(cycles))
if (cycles > 1000):
veri.finish()
rst_n = veri.peek('tb.rst_n')
if (rst_n != '1'):
return
def bitarray(self):
Now = veri.peek('%s.bitarray' % (self.Path))
if Now != self.Was:
for ii, newBit in enumerate(Now):
oldBit = self.Was[ii]
if newBit != oldBit:
logs.log_info3('catchBitWrite %s bit=%d new=%s' %
(self.Name, 31 - ii, newBit))
self.Was = Now
def peekBus(Bus, Wid, Base=''):
Res = ''
for Ind in range(Wid - 1, -1, -1):
Sig = '%s[%d]' % (Bus, Ind)
X = veri.peek('%s%s' % (Base, Sig))
Res += X
Res = Res.replace('z', '0')
Res = Res.replace('x', '0')
return int(Res, 2)
def peeksigned(Sig):
Str = veri.peek(Sig)
X = intx(Str)
if 'x' in Str: return 9999
if 'z' in Str: return 9999
if Str[0] == '0': return X
if len(Str) == 1: return X
Base = 1 << len(Str)
Res = X - Base
return Res
def pclk():
if veri.peek('tb.pready') == '0':
veri.force('tb.psel', '0')
veri.force('tb.penable', '0')
return
prdata = logs.peek('tb.prdata')
veri.force('tb.psel', '1')
veri.force('tb.penable', '1')
Exp = Expecteds.pop(0)
logs.log_info('RESULT %d exp %d' % (prdata, Exp))
def __init__(self, Path, Prefix, Monitors, Print=False):
self.Prefix = Prefix
self.Path = Path
self.Active = False
self.Print = Print
self.Ram = {}
Full = '%s.%s_%s' % (self.Path, self.Prefix, 'outputs')
Full = veri.peek(Full)
self.dataWidth = len(Full)
Full = '%s.%s_%s' % (self.Path, self.Prefix, 'inputs')
Full = veri.peek(Full)
Len = len(Full)
if Len > (self.dataWidth * 2):
self.addrWidth = Len - 2 - (self.dataWidth * 2)
self.Bweb = True
else:
self.addrWidth = Len - 2 - (self.dataWidth)
self.Bweb = False
Monitors.append(self)
logs.log_info('ramMonitor setup %s bweb=%s dataw=%d addrw=%d' %
(self.Prefix, self.Bweb, self.dataWidth, self.addrWidth))
def run(self):
if self.state == 'idle':
if self.queue != []:
self.Tms, self.Tdi, self.Catch = self.queue.pop(0)
if self.Tms == 'force':
veri.force(self.Tdi, str(self.Catch))
return
if self.Tms == 'label':
self.Catch.write('%s\n' % self.Tdi)
return
if self.Tms == 'finish':
logs.log_info('finishing from jtag sequence')
# self.Catch.write(self.Tdi)
veri.finish()
return
self.force(self.jtck, 0)
self.force(self.jtms, self.Tms)
self.force(self.jtdi, self.Tdi)
self.state = 'step0'
else:
self.force(self.jtck, 0)
self.force(self.jtms, 0)
self.force(self.jtdi, 0)
return
elif self.state == 'step0':
self.force(self.jtck, 1)
self.state = 'step1'
elif self.state == 'step1':
self.force(self.jtck, 0)
if self.Catch == 1:
self.responce = veri.peek(
'%s.%s' % (self.Path, self.jtdo)) + self.responce
elif self.Catch == 'x':
self.responce = 'X' + self.responce
elif self.responce != '':
(Cmd, Val, Len) = self.commands.pop(0)
RR = logs.intx(self.responce)
try:
logs.log_info('jtag RES 0x%x %s %x %s %x %s lastir=(%x)' %
(RR, self.responce, logs.intx(self.responce),
Cmd, Val, Len[0], Len[1]))
except:
logs.log_info('jtag RES 0x%x %s %s %s (x) %s lastir=(%s)' %
(RR, self.responce, Cmd, Val, Len, Len))
if self.callback:
self.callback(logs.intx(self.responce), Cmd, Val, Len)
self.responce = ''
else:
self.responce = ''
self.state = 'idle'
def negedge():
global cycles
cycles += 1
veri.force('tb.cycles',str(cycles))
if (cycles>2000):
veri.finish()
rst_n = veri.peek('tb.rst_n')
if (rst_n!='1'):
return
if (cycles==30):
veri.listing('tb','100','deep.list')
if (cycles>30):
for Mon in Monitors: Mon.run()
def negedge():
global cycles
rst_n = veri.peek('tb.rst_n')
if (rst_n != '1'):
return
cycles += 1
veri.force('tb.cycles', str(cycles))
if (cycles == 10):
veri.force('tb.errors', '0')
veri.force('tb.corrects', '0')
veri.force('tb.wrongs', '0')
if (cycles > 10):
monitors()
apb.run()
def negedge():
global cycles
cycles += 1
veri.force('tb.cycles', str(cycles))
rst_n = veri.peek('tb.rst_n')
if (rst_n != '1'):
return
uartmodel.run()
if txqueue != []:
tx_empty = veri.peek('tb.tx_empty0')
if tx_empty == '1':
Chr = str(txqueue.pop(0))
veri.force('tb.write_tx0', '1')
veri.force('tb.txdata0', Chr)
else:
veri.force('tb.write_tx0', '0')
else:
veri.force('tb.write_tx0', '0')
rx_valid0 = veri.peek('tb.rx_valid0')
if rx_valid0 == '1':
rxdata = veri.peek('tb.rxdata0')
logs.log_info('rx: %s' % rxdata)
def negedge():
global cycles
cycles += 1
veri.force('tb.cycles',str(cycles))
if (cycles>GIVEUP_TIMEOUT):
logs.log_info('finishing on default guard of %d'%GIVEUP_TIMEOUT)
veri.finish()
rst_n = veri.peek('tb.rst_n')
if (rst_n!='1'):
return
if (cycles==30):
veri.listing('tb','100','deep.list')
if (cycles>30):
for Mon in Monitors: Mon.run()
def run(self):
if self.Sig=='timeout':
if self.Wait<=get_cycles():
Txt = 'keepSimulationAlive decided to end this simulation, on timeout'
log_info(Txt)
if finishReason:
finishReason(Txt,Errors,Wrongs,Corrects)
veri.finish()
return 0,'timeout'
Now = veri.peek(self.Sig)
if Now != self.Val:
self.Val = Now
self.finishTime = get_cycles() + self.Wait
# log_info('advance time %s to %d'%(self.Sig,self.finishTime))
return self.finishTime,self.Sig
def run(self):
if (self.baudcount > 0):
self.baudcount -= 1
return
if (self.queue != []):
self.baudcount = self.baudrate
if self.queue[0] == 'finish':
logs.finish_now('i2c driver asked to finish')
return
(Scl, Dat) = self.queue.pop(0)
# print self.scl,Scl,self.sda_drive,Dat,len(self.queue),self.sda
veri.force(self.scl, str(Scl))
veri.force(self.sda_drive, str(Dat))
if (Scl == 0) and (Dat == 1):
Get = veri.peek(self.sda)
self.getting += Get
def run(self):
if self.Sig == 'timeout':
if self.Wait <= get_cycles():
log_info(
'keepSimulationAlive decided to end this simulation, on timeout'
)
veri.finish()
return 0, 'timeout'
Now = veri.peek(self.Sig)
if Now != self.Val:
self.Val = Now
self.finishTime = get_cycles() + self.Wait
# log_info('advance time %s to %d'%(self.Sig,self.finishTime))
return self.finishTime, self.Sig
def negedge():
global cycles
cycles += 1
veri.force('tb.cycles', str(cycles))
if (cycles > 100000):
veri.finish()
rst_n = veri.peek('tb.rst_n')
if (rst_n != '1'):
return
if (cycles == 30):
veri.listing('tb', '100', 'deep.list')
if (cycles > 30):
for Mon in Monitors:
Mon.run()
Baud = logs.peek('tb.dut.uart_baudrate')
uart.baudRate = Baud
def driveData(self, Data, Drive=True):
if not Drive:
veri.force('%s.wid_r' % self.Path, '0')
veri.force('%s.wdata_r' % self.Path, '0')
veri.force('%s.wid_r' % self.Path, '0')
veri.force('%s.wstrb_r' % self.Path, '0')
veri.force('%s.wvalid_r' % self.Path, '0')
veri.force('%s.wlast_r' % self.Path, '0')
return True
md_bready = veri.peek('%s.md_bready' % self.Path)
if md_bready == '0': return False
veri.force('%s.wdata_r' % self.Path, str(Data))
veri.force('%s.wid_r' % self.Path, '0')
veri.force('%s.wstrb_r' % self.Path, '0xff')
veri.force('%s.wvalid_r' % self.Path, '1')
veri.force('%s.wlast_r' % self.Path, '1')
return True