def mkStencilPipeline2D(coe=None, size=3, width=32, point=16):
# size-port stream inputs
iports = [dataflow.Variable('idata%d' % i, valid='ivalid%d' % i,
width=width, point=point, signed=True)
for i in range(size)]
if coe is None:
coe = [[dataflow.Constant(1.0 / (1.0 * size * size), point=point) for i in range(size)]
for j in range(size)]
# source data
data = [[d.prev(j) for j in range(size)] for d in iports]
# from 2D list to 1D list
data_list = []
coe_list = []
for d, c in zip(data, coe):
data_list.extend(d)
coe_list.extend(c)
# computation by calling standard method
rslt = stencil(coe_list, data_list)
rslt.output('odata', valid='ovalid')
df = dataflow.Dataflow(rslt)
m = df.to_module('stencil_pipeline_2d')
# try:
# df.draw_graph()
# except:
# print('Dataflow graph could not be generated.', file=sys.stderr)
return m
def mkMain():
# input variiable
x = dataflow.Variable('xdata', valid='xvalid', ready='xready', signed=True)
y = dataflow.Variable('ydata', valid='yvalid', ready='yready', signed=True)
# dataflow definition
z = x - y + dataflow.Constant(5)
z = dataflow.Sign(z)
# set output attribute
z.output('zdata', valid='zvalid', ready='zready')
df = dataflow.Dataflow(z)
m = df.to_module('main')
return m
def mkStencil(n=16, size=3, datawidth=32, point=16, coe_test=False):
m = Module('stencil')
addrwidth = int(math.log(n, 2))
clk = m.Input('CLK')
rst = m.Input('RST')
start = m.Input('start')
busy = m.OutputReg('busy', initval=0)
done = m.TmpReg(initval=0)
# external RAM I/F
ext_src_rams = [
ram.RAMSlaveInterface(m,
'ext_src_ram%d' % i,
datawidth=datawidth,
addrwidth=addrwidth) for i in range(size)
]
ext_dst_ram = ram.RAMSlaveInterface(m,
'ext_dst_ram',
datawidth=datawidth,
addrwidth=addrwidth)
# RAM
addrwidth = int(math.log(n, 2)) * 2
src_rams = [
RAM(m,
'src_ram%d' % i,
clk,
rst,
datawidth=datawidth,
addrwidth=addrwidth,
numports=2) for i in range(size)
]
dst_ram = RAM(m,
'dst_ram',
clk,
rst,
datawidth=datawidth,
addrwidth=addrwidth,
numports=2)
# connect RAM I/Fs
for src_ram, ext_src_ram in zip(src_rams, ext_src_rams):
src_ram[1].connect(ext_src_ram)
dst_ram[1].connect(ext_dst_ram)
# read FSM
read_fsm = FSM(m, 'read_fsm', clk, rst)
read_count = m.Reg('read_count', 32, initval=0)
read_addr = m.Reg('read_addr', 32, initval=0)
read_fsm(read_addr(0), read_count(0), busy(0))
read_fsm.If(start)(busy(1))
read_fsm.Then().goto_next()
read_fsm(read_addr.inc(), read_count.inc())
idata = []
ivalid = []
for i, src_ram in enumerate(src_rams):
src_ram.disable_write(0)
rdata, rvalid = src_ram.read_rtl(read_addr, port=0, cond=read_fsm)
idata.append(rdata)
ivalid.append(rvalid)
read_fsm.If(read_count == n - 1)(read_addr(0), read_count(0))
read_fsm.Then().goto_next()
read_fsm.If(done)(busy(0))
read_fsm.Then().goto_init()
read_fsm.make_always()
# instance
odata = m.Wire('odata', datawidth)
ovalid = m.Wire('ovalid')
ports = []
ports.append(('CLK', clk))
ports.append(('RST', rst))
for i, (d, v) in enumerate(zip(idata, ivalid)):
ports.append(('idata%d' % i, d))
ports.append(('ivalid%d' % i, v))
ports.append(('odata', odata))
ports.append(('ovalid', ovalid))
coe = None
if coe_test:
coe = [[dataflow.Constant(1, point=point) for i in range(size)]
for j in range(size)]
point = 0
st = mkStencilPipeline2D(size=3, width=datawidth, point=point, coe=coe)
m.Instance(st, 'inst_stencil', ports=ports)
skip_offset = int(math.floor(size / 2))
# write FSM
write_fsm = FSM(m, 'write_fsm', clk, rst)
write_count = m.Reg('write_count', 32, initval=0)
write_addr = m.Reg('write_addr', 32, initval=skip_offset)
write_fsm(done(0))
write_fsm.If(Ands(ovalid, write_count > skip_offset))(write_addr.inc())
dst_ram.write_rtl(write_addr, odata, port=0, cond=write_fsm.then)
write_fsm.If(ovalid)(write_count.inc(), )
write_fsm.If(write_count == n)(write_count(0), write_addr(skip_offset),
done(1))
write_fsm.Then().goto_init()
write_fsm.make_always()
return m