def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numbanks = 4
myram = vthread.MultibankRAM(m,
'myram',
clk,
rst,
datawidth,
addrwidth,
numbanks=numbanks)
def blink(times):
for i in range(times * numbanks):
wdata = i
myram.write(i, wdata)
print('wdata = %d' % wdata)
sum = 0
for i in range(times * numbanks):
rdata = myram.read(i)
sum += rdata
print('rdata = %d' % rdata)
print('sum = %d' % sum)
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(10)
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numbanks = 4
myram = vthread.MultibankRAM(m,
'myram',
clk,
rst,
datawidth,
addrwidth,
numbanks=numbanks)
def blink(times):
all_ok = True
write_sum = 0
wdata = 0
for i in range(times):
for b in range(numbanks):
myram.write_bank(b, i, wdata)
print('bank:%d wdata = %d' % (b, wdata))
write_sum += wdata
wdata += 1
print('write_sum = %d' % write_sum)
read_sum = 0
expected = 0
for i in range(times):
for b in range(numbanks):
rdata = myram.read_bank(b, i)
read_sum += rdata
print('bank:%d rdata = %d' % (b, rdata))
if vthread.verilog.NotEql(rdata, expected):
all_ok = False
expected += 1
print('read_sum = %d' % read_sum)
if vthread.verilog.NotEql(read_sum, write_sum):
all_ok = False
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(10)
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numbanks = 4
myram = vthread.MultibankRAM(m,
'myram',
clk,
rst,
datawidth,
addrwidth,
numbanks=numbanks,
ram_style='(* ram_style = "block" *)')
def blink(times):
all_ok = True
write_sum = 0
for i in range(times * numbanks):
wdata = i
myram.write(i, wdata)
write_sum += wdata
print('wdata = %d' % wdata)
read_sum = 0
for i in range(times * numbanks):
rdata = myram.read(i)
read_sum += rdata
print('rdata = %d' % rdata)
print('read_sum = %d' % read_sum)
if vthread.verilog.NotEql(read_sum, write_sum):
all_ok = False
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(10)
return m
def mkLed(memory_datawidth=128):
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numbanks = 4
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, memory_datawidth)
myrams = [vthread.RAM(m, 'myram_%d' % i, clk, rst, datawidth, addrwidth)
for i in range(numbanks)]
myram = vthread.MultibankRAM(rams=myrams, name='myram')
all_ok = m.TmpReg(initval=0)
array_len = 16
array_size = (array_len + array_len) * 4 * numbanks
def blink(size):
all_ok.value = True
for i in range(4):
print('# iter %d start' % i)
# Test for 4KB boundary check
offset = i * 1024 * 16 + (myaxi.boundary_size - 4)
body(size, offset)
print('# iter %d end' % i)
if all_ok:
print('ALL OK')
def body(size, offset):
# write
for bank in range(numbanks):
for i in range(size):
wdata = i + 100 + bank
myram.write_bank(bank, i, wdata)
laddr = 0
gaddr = offset
myaxi.dma_write(myram, laddr, gaddr, size)
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
# write
for bank in range(numbanks):
for i in range(size):
wdata = i + 1000 + bank
myram.write_bank(bank, i, wdata)
laddr = 0
gaddr = array_size + offset
myaxi.dma_write(myram, laddr, gaddr, size)
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
# read
laddr = 0
gaddr = offset
myaxi.dma_read(myram, laddr, gaddr, size)
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
for bank in range(numbanks):
for i in range(size):
rdata = myram.read_bank(bank, i)
if vthread.verilog.NotEql(rdata, i + 100 + bank):
print('rdata[%d] = %d' % (i, rdata))
all_ok.value = False
# read
laddr = 0
gaddr = array_size + offset
myaxi.dma_read(myram, laddr, gaddr, size)
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
for bank in range(numbanks):
for i in range(size):
rdata = myram.read_bank(bank, i)
if vthread.verilog.NotEql(rdata, i + 1000 + bank):
print('rdata[%d] = %d' % (i, rdata))
all_ok.value = False
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(array_len)
return m
def mkLed(memory_datawidth=128):
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numbanks = 4
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, memory_datawidth)
ram_a = vthread.MultibankRAM(m,
'ram_a',
clk,
rst,
datawidth,
addrwidth,
numbanks=numbanks)
ram_b = vthread.MultibankRAM(m,
'ram_b',
clk,
rst,
datawidth,
addrwidth,
numbanks=numbanks)
ram_c = vthread.MultibankRAM(m,
'ram_c',
clk,
rst,
datawidth,
addrwidth,
numbanks=numbanks)
strm = vthread.Stream(m, 'mystream', clk, rst)
a = strm.source('a')
b = strm.source('b')
c = a + b
strm.sink(c, 'c')
def comp_stream(size, offset):
strm.set_source('a', ram_a, offset, size)
strm.set_source('b', ram_b, offset, size)
strm.set_sink('c', ram_c, offset, size)
strm.run()
strm.join()
def comp_sequential(size, offset):
sum = 0
for i in range(size):
a = ram_a.read(i + offset)
b = ram_b.read(i + offset)
sum = a + b
ram_c.write(i + offset, sum)
def check(size, offset_stream, offset_seq):
all_ok = True
for i in range(size):
st = ram_c.read(i + offset_stream)
sq = ram_c.read(i + offset_seq)
if vthread.verilog.NotEql(st, sq):
all_ok = False
print(i, st, sq)
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
def comp(size):
dma_size = size
comp_size = size * numbanks
dma_offset = 0
comp_offset = 0
myaxi.dma_read(ram_a, dma_offset, 0, dma_size)
myaxi.dma_read(ram_b, dma_offset, 0, dma_size)
comp_stream(size, comp_offset)
myaxi.dma_write(ram_c, dma_offset, 1024, dma_size)
dma_offset = size
comp_offset = comp_size
myaxi.dma_read(ram_a, dma_offset, 0, dma_size)
myaxi.dma_read(ram_b, dma_offset, 0, dma_size)
comp_sequential(size, comp_offset)
myaxi.dma_write(ram_c, dma_offset, 1024 * 2, dma_size)
check(comp_size, 0, comp_offset)
vthread.finish()
th = vthread.Thread(m, 'th_comp', clk, rst, comp)
fsm = th.start(32)
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numbanks = 4
ram_addrwidth = addrwidth - int(math.log(addrwidth, 2))
myram = vthread.MultibankRAM(m, 'myram', clk, rst, datawidth, ram_addrwidth,
numbanks=numbanks, numports=2)
read_size = 10
write_size = read_size
write_done = m.Reg('write_done', initval=0)
addr = m.Reg('addr', addrwidth, initval=0)
wdata = m.Reg('wdata', datawidth, initval=0)
wenable = m.Reg('wenable', initval=0)
rdata = m.Wire('rdata', datawidth)
sum = m.Reg('sum', datawidth, initval=0)
fsm = FSM(m, 'fsm', clk, rst)
fsm.If(write_done).goto_next()
# write
fsm(
addr(-1),
wdata(-1),
wenable(0)
)
fsm.goto_next()
fsm(
addr.inc(),
wdata.inc(),
wenable(1)
)
fsm.Delay(1)(
Display('wdata = %d', wdata),
wenable(0)
)
fsm.If(addr == write_size - 2).goto_next()
# read
fsm(
addr(-1),
wenable(0)
)
fsm.goto_next()
fsm(
addr.inc()
)
fsm.Delay(2)(
sum.add(rdata),
Display('rdata = %d', rdata)
)
fsm.If(addr == read_size - 2).goto_next()
fsm.goto_next()
fsm.goto_next()
# sum
fsm(
Display('sum = %d', sum)
)
fsm.goto_next()
# connect ports to RAM
myram.connect_rtl(1, addr, wdata, wenable, rdata)
def blink(times):
write_done.value = 0
for i in range(times):
wdata = i + 100
myram.write(i, wdata)
print('wdata = %d' % wdata)
write_done.value = 1
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(read_size)
return m
def mkLed(memory_datawidth=32):
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numbanks = 4
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, memory_datawidth)
myram = vthread.MultibankRAM(m,
'myram',
clk,
rst,
datawidth,
addrwidth,
numbanks=numbanks)
all_ok = m.TmpReg(initval=0)
block_size = 3
array_len = 32
array_size = (array_len + array_len) * 4 * numbanks
def blink(size):
all_ok.value = True
print('# start')
# Test for 4KB boundary check
#offset = 1024 * 16 + (myaxi.boundary_size - 4)
offset = 1024 * 16
body(size, offset)
print('# end')
if all_ok:
print('ALL OK')
def body(size, offset):
# write
count = 0
blk_offset = 0
bias = 0
done = False
while count < size:
for bank in range(numbanks):
for i in range(block_size):
wdata = bias + i + 512
myram.write_bank(bank, blk_offset + i, wdata)
count += 1
if count >= size:
done = True
break
if done:
break
bias += block_size
blk_offset += block_size
laddr = 0
gaddr = offset
myram.dma_write_block(myaxi, laddr, gaddr, size, block_size)
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
# write
count = 0
blk_offset = 0
bias = 0
done = False
while count < size:
for bank in range(numbanks):
for i in range(block_size):
wdata = bias + i + 1024
myram.write_bank(bank, blk_offset + i, wdata)
count += 1
if count >= size:
done = True
break
if done:
break
bias += block_size
blk_offset += block_size
laddr = 0
gaddr = array_size + offset
myram.dma_write_block(myaxi, laddr, gaddr, size, block_size)
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
# read
laddr = 0
gaddr = offset
myram.dma_read_block(myaxi, laddr, gaddr, size, block_size)
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
count = 0
blk_offset = 0
bias = 0
done = False
while count < size:
for bank in range(numbanks):
for i in range(block_size):
rdata = myram.read_bank(bank, blk_offset + i)
exp = bias + i + 512
if vthread.verilog.NotEql(rdata, exp):
print('rdata[%d:%d] = %d:%d' % (bank, i, rdata, exp))
all_ok.value = False
count += 1
if count >= size:
done = True
break
if done:
break
bias += block_size
blk_offset += block_size
# read
laddr = 0
gaddr = array_size + offset
myram.dma_read_block(myaxi, laddr, gaddr, size, block_size)
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
count = 0
blk_offset = 0
bias = 0
done = False
while count < size:
for bank in range(numbanks):
for i in range(block_size):
rdata = myram.read_bank(bank, blk_offset + i)
exp = bias + i + 1024
if vthread.verilog.NotEql(rdata, exp):
print('rdata[%d:%d] = %d:%d' % (bank, i, rdata, exp))
all_ok.value = False
count += 1
if count >= size:
done = True
break
if done:
break
bias += block_size
blk_offset += block_size
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(array_len)
return m
def mkLed():
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numbanks = 4
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
myram = vthread.MultibankRAM(m,
'myram',
clk,
rst,
datawidth,
addrwidth,
numbanks=numbanks)
all_ok = m.TmpReg(initval=0)
def blink(size):
all_ok.value = True
for i in range(4):
print('# iter %d start' % i)
# Test for 4KB boundary check
offset = i * 1024 * 16 + (myaxi.boundary_size - 4)
for bank in range(numbanks):
bank_offset = offset + bank * 1024
body(bank, size, bank_offset)
print('# iter %d end' % i)
if all_ok:
print('ALL OK')
def body(bank, size, offset):
# write
for i in range(size):
wdata = i + 100
myram.write_bank(bank, i, wdata)
laddr = 0
gaddr = offset
myram.dma_write_bank(bank, myaxi, laddr, gaddr, size)
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
# write
for i in range(size):
wdata = i + 1000
myram.write_bank(bank, i, wdata)
laddr = 0
gaddr = (size + size) * 4 + offset
myram.dma_write_bank(bank, myaxi, laddr, gaddr, size)
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
# read
laddr = 0
gaddr = offset
myram.dma_read_bank(bank, myaxi, laddr, gaddr, size)
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
for i in range(size):
rdata = myram.read_bank(bank, i)
if vthread.verilog.NotEql(rdata, i + 100):
print('rdata[%d] = %d' % (i, rdata))
all_ok.value = False
# read
laddr = 0
gaddr = (size + size) * 4 + offset
myram.dma_read_bank(bank, myaxi, laddr, gaddr, size)
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
for i in range(size):
rdata = myram.read_bank(bank, i)
if vthread.verilog.NotEql(rdata, i + 1000):
print('rdata[%d] = %d' % (i, rdata))
all_ok.value = False
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(16)
return m
def mkLed(axi_datawidth=32, datawidth=4, addrwidth=10):
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
numbanks = int(math.ceil(axi_datawidth / datawidth))
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, axi_datawidth)
myram = vthread.MultibankRAM(m,
'myram',
clk,
rst,
datawidth,
addrwidth,
numbanks=numbanks)
saxi = vthread.AXISLiteRegister(m, 'saxi', clk, rst, 32)
all_ok = m.TmpReg(initval=0)
def blink(size):
# wait start
saxi.wait_flag(0, value=1, resetvalue=0)
# reset done
saxi.write(1, 0)
all_ok.value = True
for i in range(4):
print('# iter %d start' % i)
# Test for 4KB boundary check
offset = i * 1024 * 16 + (myaxi.boundary_size - 4)
body(size, offset)
print('# iter %d end' % i)
if all_ok:
print('# verify (local): PASSED')
else:
print('# verify (local): FAILED')
# result
saxi.write(2, all_ok)
# done
saxi.write_flag(1, 1, resetvalue=0)
def body(size, offset):
# write
for i in range(size):
wdata = (i + 100) % (2**datawidth)
myram.write(i, wdata)
laddr = 0
gaddr = offset
myaxi.dma_write(myram, laddr, gaddr, size)
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
# write
for i in range(size):
wdata = (i + 1000) % (2**datawidth)
myram.write(i, wdata)
laddr = 0
gaddr = (size + size) * 4 + offset
myaxi.dma_write(myram, laddr, gaddr, size)
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
# read
laddr = 0
gaddr = offset
myaxi.dma_read(myram, laddr, gaddr, size)
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
for i in range(size):
rdata = myram.read(i) & (2**datawidth - 1)
verify = (i + 100) % (2**datawidth)
if vthread.verilog.NotEql(rdata, verify):
print('rdata[%d] = %d (!= %d)' % (i, rdata, verify))
all_ok.value = False
# read
laddr = 0
gaddr = (size + size) * 4 + offset
myaxi.dma_read(myram, laddr, gaddr, size)
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
for i in range(size):
rdata = myram.read(i) & (2**datawidth - 1)
verify = (i + 1000) % (2**datawidth)
if vthread.verilog.NotEql(rdata, verify):
print('rdata[%d] = %d (!= %d)' % (i, rdata, verify))
all_ok.value = False
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(16)
return m
def mkLed(memory_datawidth=128):
m = Module('blinkled')
clk = m.Input('CLK')
rst = m.Input('RST')
datawidth = 32
addrwidth = 10
numbanks = 4
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, memory_datawidth)
myram = vthread.MultibankRAM(m,
'myram',
clk,
rst,
datawidth,
addrwidth,
numbanks=numbanks)
all_ok = m.TmpReg(initval=0)
array_len = 256 + 128
array_size = (array_len + array_len) * 4 * numbanks
def blink(size):
all_ok.value = True
offset = 1024 * 16
body(size, offset)
if all_ok:
print('# verify: PASSED')
else:
print('# verify: FAILED')
vthread.finish()
def body(size, offset):
# write
for bank in range(numbanks):
for i in range(size):
wdata = i + 100 + bank
myram.write_bank(bank, i, wdata)
laddr = 0
gaddr = offset
myaxi.dma_write(myram, laddr, gaddr, size)
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
# write
for bank in range(numbanks):
for i in range(size):
wdata = i + 1000 + bank
myram.write_bank(bank, i, wdata)
laddr = 0
gaddr = array_size + offset
myaxi.dma_write(myram, laddr, gaddr, size)
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
# read
laddr = 0
gaddr = offset
myaxi.dma_read(myram, laddr, gaddr, size)
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
for bank in range(numbanks):
for i in range(size):
rdata = myram.read_bank(bank, i)
if vthread.verilog.NotEql(rdata, i + 100 + bank):
print('rdata[%d] = %d' % (i, rdata))
all_ok.value = False
# read
laddr = 0
gaddr = array_size + offset
myaxi.dma_read(myram, laddr, gaddr, size)
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
for bank in range(numbanks):
for i in range(size):
rdata = myram.read_bank(bank, i)
if vthread.verilog.NotEql(rdata, i + 1000 + bank):
print('rdata[%d] = %d' % (i, rdata))
all_ok.value = False
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
fsm = th.start(array_len)
return m
