def mkLed():
m = Module('blinkled')
width = m.Parameter('WIDTH', 8)
clk = m.Input('CLK')
rst = m.Input('RST')
led = m.OutputReg('LED', width)
count = m.Reg('count', 32)
m.Always(Posedge(clk))(If(rst)(count(0)).Else(
If(count == 1023)(count(0)).Else(count(count + 1))))
m.Always(Posedge(clk))(If(rst)(led(0)).Else(
If(count == 1024 - 1)(led(led + 1))))
a = fixed.FixedReg(m, 'a', point=4)
b = fixed.FixedReg(m, 'b', point=8)
c = fixed.FixedReg(m, 'c', point=16)
d = fixed.FixedReg(m, 'd', point=6)
sa = fixed.FixedReg(m, 'sa', point=4, signed=True)
sb = fixed.FixedReg(m, 'sb', point=8, signed=True)
sc = fixed.FixedReg(m, 'sc', point=16, signed=True)
sd = fixed.FixedReg(m, 'sd', point=6, signed=True)
m.Always(Posedge(clk))(If(rst)(a(fixed.FixedConst(1, 4)),
b(fixed.FixedConst(32, 4, raw=True)),
c(fixed.FixedConst(32, 4, raw=True)),
d(fixed.FixedConst(32, 4, raw=True)),
sa(fixed.FixedConst(1, 4)),
sb(fixed.FixedConst(32, 4, raw=True)),
sc(fixed.FixedConst(32, 4, raw=True)),
sd(fixed.FixedConst(32, 4, raw=True))).Else(
a(a / b), b(a / b), c(a / b), d(b / a),
sa(sa / sb), sb(sa / sb), sc(sa / sb),
sd(sb / sa)))
return m
def FixedConst(fsm, value, point=0, signed=True, raw=False):
point = vtypes.raw_value(point)
return fixed.FixedConst(value, point, signed, raw)
def mkTest(n=16, size=3, datawidth=32, point=16, coe_test=False):
if coe_test:
point = 0
m = Module('test')
addrwidth = int(math.log(n, 2))
main = mkStencil(n, size, datawidth, point, coe_test)
params = m.copy_params(main)
ports = m.copy_sim_ports(main)
clk = ports['CLK']
rst = ports['RST']
start = ports['start']
busy = ports['busy']
uut = m.Instance(main,
'uut',
params=m.connect_params(main),
ports=m.connect_ports(main))
reset_done = m.Reg('reset_done', initval=0)
reset_stmt = []
reset_stmt.append(reset_done(0))
reset_stmt.append(start(0))
# src RAM
for i in range(3):
addr = ports['ext_src_ram%d_addr' % i]
rdata = ports['ext_src_ram%d_rdata' % i]
wdata = ports['ext_src_ram%d_wdata' % i]
wenable = ports['ext_src_ram%d_wenable' % i]
reset_stmt.append(addr(0))
reset_stmt.append(wdata(0))
reset_stmt.append(wenable(0))
# dst RAM
addr = ports['ext_dst_ram_addr']
rdata = ports['ext_dst_ram_rdata']
wdata = ports['ext_dst_ram_wdata']
wenable = ports['ext_dst_ram_wenable']
reset_stmt.append(addr(2))
reset_stmt.append(wdata(0))
reset_stmt.append(wenable(0))
simulation.setup_waveform(m, uut)
simulation.setup_clock(m, clk, hperiod=5)
init = simulation.setup_reset(m, rst, reset_stmt, period=100)
nclk = simulation.next_clock
init.add(
Delay(1000),
reset_done(1),
nclk(clk),
Delay(100000),
Systask('finish'),
)
fsm = FSM(m, 'fsm', clk, rst)
fsm.goto_next(cond=reset_done)
for i in range(3):
addr = ports['ext_src_ram%d_addr' % i]
fsm.add(addr(-1))
fsm.goto_next()
for i in range(3):
addr = ports['ext_src_ram%d_addr' % i]
rdata = ports['ext_src_ram%d_rdata' % i]
wdata = ports['ext_src_ram%d_wdata' % i]
wenable = ports['ext_src_ram%d_wenable' % i]
next_addr = (addr + 1) % (n * n)
fsm.add(addr.inc())
fsm.add(wdata(fixed.FixedConst(90, point).raw))
fsm.add(wenable(1))
fsm.add(wenable(0), cond=AndList(wenable, addr == 2**addrwidth - 1))
fsm.goto_next(
cond=AndList(wenable, ports['ext_src_ram0_addr'] == 2**addrwidth - 1))
fsm.goto_next(cond=Not(busy))
fsm.add(start(1))
fsm.add(start(0), delay=1)
fsm.goto_next()
fsm.goto_next(cond=busy)
fsm.goto_next(cond=Not(busy))
fsm.add(Systask('finish'))
fsm.make_always()
return m