def test_arbitrary_pipeline():
if reset == reset.active:
for _A, _B, _opmode in zip(A_pipeline, B_pipeline,
opmode_pipeline):
_A.next = _A._init
_B.next = _B._init
_opmode.next = _opmode._init
P.next = P._init
else:
if clock_enable:
A_pipeline.append(copy_signal(A))
B_pipeline.append(copy_signal(B))
opmode_pipeline.append(copy_signal(opmode))
A_out = A_pipeline.popleft()
B_out = B_pipeline.popleft()
opmode_out = opmode_pipeline.popleft()
P.next = A_out * B_out
else:
# Nothing changes
pass
def test_arbitrary_pipeline():
if reset == reset.active:
for _A, _B, _opmode in zip(
A_pipeline, B_pipeline, opmode_pipeline):
_A.next = _A._init
_B.next = _B._init
_opmode.next = _opmode._init
P.next = P._init
else:
if clock_enable:
A_pipeline.append(copy_signal(A))
B_pipeline.append(copy_signal(B))
opmode_pipeline.append(copy_signal(opmode))
A_out = A_pipeline.popleft()
B_out = B_pipeline.popleft()
opmode_out = opmode_pipeline.popleft()
P.next = A_out * B_out
else:
# Nothing changes
pass
def test_arbitrary_pipeline():
if reset == reset.active:
for _A, _B, _C, _opmode in zip(A_pipeline, B_pipeline,
C_pipeline,
opmode_pipeline):
_A.next = _A._init
_B.next = _B._init
_C.next = _C._init
_opmode.next = _opmode._init
P.next = P._init
else:
A_pipeline.append(copy_signal(A))
B_pipeline.append(copy_signal(B))
C_pipeline.append(copy_signal(C))
opmode_pipeline.append(copy_signal(opmode))
A_out = A_pipeline.popleft()
B_out = B_pipeline.popleft()
C_out = C_pipeline.popleft()
opmode_out = opmode_pipeline.popleft()
if (opmode_reverse_lookup[int(
opmode_out.val)] == 'multiply'):
P.next = A_out * B_out
elif (opmode_reverse_lookup[int(
opmode_out.val)] == 'multiply_add'):
P.next = A_out * B_out + C_out
if (opmode_reverse_lookup[int(
opmode_out.val)] == 'multiply_accumulate'):
P.next = A_out * B_out + P
def ref(**kwargs):
P = kwargs['P']
A = kwargs['A']
B = kwargs['B']
C = kwargs['C']
opmode = kwargs['opmode']
clock = kwargs['clock']
reset = kwargs['reset']
# Each pipeline should be pipeline_registers - 1 long since
# there is one implicit register.
A_pipeline = deque(
[copy_signal(A) for _ in range(self.pipeline_registers - 1)])
B_pipeline = deque(
[copy_signal(B) for _ in range(self.pipeline_registers - 1)])
C_pipeline = deque(
[copy_signal(C) for _ in range(self.pipeline_registers - 1)])
opmode_pipeline = deque([
copy_signal(opmode) for _ in range(self.pipeline_registers - 1)
])
@always(clock.posedge)
def test_arbitrary_pipeline():
if reset == reset.active:
for _A, _B, _C, _opmode in zip(A_pipeline, B_pipeline,
C_pipeline,
opmode_pipeline):
_A.next = _A._init
_B.next = _B._init
_C.next = _C._init
_opmode.next = _opmode._init
P.next = P._init
else:
A_pipeline.append(copy_signal(A))
B_pipeline.append(copy_signal(B))
C_pipeline.append(copy_signal(C))
opmode_pipeline.append(copy_signal(opmode))
A_out = A_pipeline.popleft()
B_out = B_pipeline.popleft()
C_out = C_pipeline.popleft()
opmode_out = opmode_pipeline.popleft()
if (opmode_reverse_lookup[int(
opmode_out.val)] == 'multiply'):
P.next = A_out * B_out
elif (opmode_reverse_lookup[int(
opmode_out.val)] == 'multiply_add'):
P.next = A_out * B_out + C_out
if (opmode_reverse_lookup[int(
opmode_out.val)] == 'multiply_accumulate'):
P.next = A_out * B_out + P
return test_arbitrary_pipeline
def ref(**kwargs):
P = kwargs['P']
A = kwargs['A']
B = kwargs['B']
opmode = kwargs['opmode']
clock_enable = kwargs['clock_enable']
clock = kwargs['clock']
reset = kwargs['reset']
# Each pipeline should be pipeline_registers - 1 long since
# there is one implicit register.
A_pipeline = deque(
[copy_signal(A) for _ in range(self.pipeline_registers - 1)])
B_pipeline = deque(
[copy_signal(B) for _ in range(self.pipeline_registers - 1)])
opmode_pipeline = deque([
copy_signal(opmode) for _ in range(self.pipeline_registers - 1)
])
@always(clock.posedge)
def test_arbitrary_pipeline():
if reset == reset.active:
for _A, _B, _opmode in zip(A_pipeline, B_pipeline,
opmode_pipeline):
_A.next = _A._init
_B.next = _B._init
_opmode.next = _opmode._init
P.next = P._init
else:
if clock_enable:
A_pipeline.append(copy_signal(A))
B_pipeline.append(copy_signal(B))
opmode_pipeline.append(copy_signal(opmode))
A_out = A_pipeline.popleft()
B_out = B_pipeline.popleft()
opmode_out = opmode_pipeline.popleft()
P.next = A_out * B_out
else:
# Nothing changes
pass
return test_arbitrary_pipeline
def ref(**kwargs):
P = kwargs['P']
A = kwargs['A']
B = kwargs['B']
opmode = kwargs['opmode']
clock_enable = kwargs['clock_enable']
clock = kwargs['clock']
reset = kwargs['reset']
# Each pipeline should be pipeline_registers - 1 long since
# there is one implicit register.
A_pipeline = deque(
[copy_signal(A) for _ in range(self.pipeline_registers - 1)])
B_pipeline = deque(
[copy_signal(B) for _ in range(self.pipeline_registers - 1)])
opmode_pipeline = deque(
[copy_signal(opmode) for _ in
range(self.pipeline_registers - 1)])
@always(clock.posedge)
def test_arbitrary_pipeline():
if reset == reset.active:
for _A, _B, _opmode in zip(
A_pipeline, B_pipeline, opmode_pipeline):
_A.next = _A._init
_B.next = _B._init
_opmode.next = _opmode._init
P.next = P._init
else:
if clock_enable:
A_pipeline.append(copy_signal(A))
B_pipeline.append(copy_signal(B))
opmode_pipeline.append(copy_signal(opmode))
A_out = A_pipeline.popleft()
B_out = B_pipeline.popleft()
opmode_out = opmode_pipeline.popleft()
P.next = A_out * B_out
else:
# Nothing changes
pass
return test_arbitrary_pipeline
def test_arbitrary_pipeline():
if reset == reset.active:
for _A, _B, _C, _opmode in zip(
A_pipeline, B_pipeline, C_pipeline, opmode_pipeline):
_A.next = _A._init
_B.next = _B._init
_C.next = _C._init
_opmode.next = _opmode._init
P.next = P._init
else:
if clock_enable:
A_pipeline.append(copy_signal(A))
B_pipeline.append(copy_signal(B))
C_pipeline.append(copy_signal(C))
opmode_pipeline.append(copy_signal(opmode))
A_out = A_pipeline.popleft()
B_out = B_pipeline.popleft()
C_out = C_pipeline.popleft()
opmode_out = opmode_pipeline.popleft()
if (opmode_reverse_lookup[int(opmode_out.val)] ==
'multiply'):
P.next = A_out * B_out
elif (opmode_reverse_lookup[int(opmode_out.val)] ==
'multiply_add'):
P.next = A_out * B_out + C_out
elif (opmode_reverse_lookup[int(opmode_out.val)] ==
'multiply_accumulate'):
P.next = P + A_out * B_out
elif (opmode_reverse_lookup[int(opmode_out.val)] ==
'multiply_deccumulate'):
P.next = P - A_out * B_out
def ref(**kwargs):
P = kwargs['P']
A = kwargs['A']
B = kwargs['B']
C = kwargs['C']
opmode = kwargs['opmode']
clock_enable = kwargs['clock_enable']
clock = kwargs['clock']
reset = kwargs['reset']
# Each pipeline should be pipeline_registers - 1 long since
# there is one implicit register.
A_pipeline = deque(
[copy_signal(A) for _ in range(self.pipeline_registers - 1)])
B_pipeline = deque(
[copy_signal(B) for _ in range(self.pipeline_registers - 1)])
C_pipeline = deque(
[copy_signal(C) for _ in range(self.pipeline_registers - 1)])
opmode_pipeline = deque(
[copy_signal(opmode) for _ in
range(self.pipeline_registers - 1)])
@always(clock.posedge)
def test_arbitrary_pipeline():
if reset == reset.active:
for _A, _B, _C, _opmode in zip(
A_pipeline, B_pipeline, C_pipeline, opmode_pipeline):
_A.next = _A._init
_B.next = _B._init
_C.next = _C._init
_opmode.next = _opmode._init
P.next = P._init
else:
if clock_enable:
A_pipeline.append(copy_signal(A))
B_pipeline.append(copy_signal(B))
C_pipeline.append(copy_signal(C))
opmode_pipeline.append(copy_signal(opmode))
A_out = A_pipeline.popleft()
B_out = B_pipeline.popleft()
C_out = C_pipeline.popleft()
opmode_out = opmode_pipeline.popleft()
if (opmode_reverse_lookup[int(opmode_out.val)] ==
'multiply'):
P.next = A_out * B_out
elif (opmode_reverse_lookup[int(opmode_out.val)] ==
'multiply_add'):
P.next = A_out * B_out + C_out
elif (opmode_reverse_lookup[int(opmode_out.val)] ==
'multiply_accumulate'):
P.next = P + A_out * B_out
elif (opmode_reverse_lookup[int(opmode_out.val)] ==
'multiply_deccumulate'):
P.next = P - A_out * B_out
return test_arbitrary_pipeline