def tixr(self): alu.addrm(reg.getRegister(reg.SICXE_NUM_REGISTER_X), self.mem, 1, True) alu.comprr(reg.getRegister(reg.SICXE_NUM_REGISTER_X), reg.getRegister(getRegister1(self.instruction)), reg.getRegister(reg.SICXE_NUM_REGISTER_SW))
def fetch(self): pc = reg.getRegister(reg.SICXE_NUM_REGISTER_PC) b = reg.getRegister(reg.SICXE_NUM_REGISTER_B) x = reg.getRegister(reg.SICXE_NUM_REGISTER_X) ta = getTargetAddress(self.instruction, pc, b, x, self.mem) return ta.dec
def tix(self): alu.addrm(reg.getRegister(reg.SICXE_NUM_REGISTER_X), self.mem, 1, True) alu.comprm(reg.getRegister(reg.SICXE_NUM_REGISTER_X), reg.getRegister(reg.SICXE_NUM_REGISTER_SW), self.mem, self.fetch(), isImidiateInstr(self.instruction))
def norm(self): reg.getRegister(reg.SICXE_NUM_REGISTER_F).normalize(setSelf=True)
def wd(self): device = self.fetch() if isImidiateInstr(self.instruction) else self.mem.getbyte(self.fetch()) self.devices[device].write(reg.getRegister(reg.SICXE_NUM_REGISTER_A))
def subr(self): alu.subrr(reg.getRegister(getRegister1(self.instruction)), reg.getRegister(getRegister2(self.instruction)))
def stx(self): alu.st(reg.getRegister(reg.SICXE_NUM_REGISTER_X), self.mem, self.fetch())
def rsub(self): reg.getRegister(reg.SICXE_NUM_REGISTER_PC).set(reg.getRegister(reg.SICXE_NUM_REGISTER_L))
def j(self): reg.getRegister(reg.SICXE_NUM_REGISTER_PC).set(self.fetch())
def float(self): reg.getRegister(reg.SICXE_NUM_REGISTER_F).set(reg.getRegister(reg.SICXE_NUM_REGISTER_A))
def fix(self): reg.getRegister(reg.SICXE_NUM_REGISTER_A).set(reg.getRegister(reg.SICXE_NUM_REGISTER_F))
def divr(self): alu.divrr(reg.getRegister(getRegister1(self.instruction)), reg.getRegister(getRegister2(self.instruction)))
def compr(self): alu.comprr(reg.getRegister(getRegister1(self.instruction)), reg.getRegister(getRegister2(self.instruction)), reg.getRegister(reg.SICXE_NUM_REGISTER_SW))
def clear(self): reg.getRegister(getRegister1(self.instruction)).set(0)
def addr(self): alu.addrr(reg.getRegister(getRegister1(self.instruction)), reg.getRegister(getRegister2(self.instruction)))
def orr(self): alu.orrm(reg.getRegister(reg.SICXE_NUM_REGISTER_A), self.mem, self.fetch(), isImidiateInstr(self.instruction))
def rmo(self): reg.getRegister(getRegister2(self.instruction)).set(reg.getRegister(getRegister1(self.instruction)))
def jlt(self): cc = reg.getRegister(reg.SICXE_NUM_REGISTER_SW).getbits((6, 8), BIG) if cc == alu.SICXE_CC_LT: self.j()
def shiftr(self): alu.shiftr(reg.getRegister(getRegister1(self.instruction)), getRegister2(self.instruction))
def setStartingAddress(self, addr): reg.getRegister(reg.SICXE_NUM_REGISTER_PC).set(addr)
def subf(self): alu.subfrm(reg.getRegister(reg.SICXE_NUM_REGISTER_F), self.mem, self.fetch(), isImidiateInstr(self.instruction))
def jne(self): cc = reg.getRegister(reg.SICXE_NUM_REGISTER_SW).getbits((6, 8), BIG) if cc != alu.SICXE_CC_EQ: self.j()
def td(self): device = self.mem.getbyte(self.fetch()) self.devices[device].test(reg.getRegister(reg.SICXE_NUM_REGISTER_SW))
def jsub(self): reg.getRegister(reg.SICXE_NUM_REGISTER_L).set(reg.getRegister(reg.SICXE_NUM_REGISTER_PC)) self.j()
def ldx(self): alu.ld(reg.getRegister(reg.SICXE_NUM_REGISTER_X), self.mem, self.fetch(), isImidiateInstr(self.instruction))
def mulr(self): alu.mulrr(reg.getRegister(getRegister1(self.instruction)), reg.getRegister(getRegister2(self.instruction)))
def ontick(self): self.instruction = self.getInstruction() pc = reg.getRegister(reg.SICXE_NUM_REGISTER_PC) pc.add(len(self.getInstruction()), setSelf=True)
def getInstruction(self): pc = reg.getRegister(reg.SICXE_NUM_REGISTER_PC) instr = self.mem.get(int(pc), 2, asbytearr=True) length = getFormat(instr) return self.mem.get(int(pc), length, asbytearr=True)