def axi_set_dq_odelay(
self,
delay=None, # input [7:0] delay;
quiet=1):
"""
Set all DQ OUTput delays to the same value
@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
if delay is None will restore default values
Alternatively it can be a one-level list/tuple covering all (16) delays
@param quiet reduce output
"""
if delay is None:
delay = [[], []]
for i in range(8):
delay[0].append(vrlg.get_default_field("DLY_LANE0_ODELAY", i))
delay[1].append(vrlg.get_default_field("DLY_LANE1_ODELAY", i))
if isinstance(delay, (int, long)):
delay = (delay, delay)
elif len(delay) % 8 == 0:
delay2 = []
for lane in range(len(delay) // 8):
delay2.append(delay[8 * lane:8 * (lane + 1)])
delay = delay2
if quiet < 2:
print("SET DQ ODELAY=" + hexMultiple(delay)) # hexMultiple
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 0, 8, delay[0],
"DLY_LANE0_ODELAY")
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 0, 8, delay[1],
"DLY_LANE1_ODELAY")
self.x393_axi_tasks.write_control_register(vrlg.DLY_SET, 0)
def axi_set_dq_odelay(self,
delay=None, # input [7:0] delay;
quiet=1):
"""
Set all DQ OUTput delays to the same value
@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
if delay is None will restore default values
Alternatively it can be a one-level list/tuple covering all (16) delays
@param quiet reduce output
"""
if delay is None:
delay=[[],[]]
for i in range(8):
delay[0].append(vrlg.get_default_field("DLY_LANE0_ODELAY",i))
delay[1].append(vrlg.get_default_field("DLY_LANE1_ODELAY",i))
if isinstance(delay,(int,long)):
delay=(delay,delay)
elif len(delay) % 8 == 0 :
delay2=[]
for lane in range(len(delay)//8):
delay2.append(delay[8*lane:8*(lane+1)])
delay=delay2
if quiet < 2:
print("SET DQ ODELAY="+hexMultiple(delay)) # hexMultiple
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 0, 8, delay[0], "DLY_LANE0_ODELAY");
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 0, 8, delay[1], "DLY_LANE1_ODELAY");
self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0); # set all delays
def axi_set_cmd_odelay(
self,
delay=None, # input [7:0] delay;
indx=None, # address index
quiet=1):
"""
Set output delays for command lines only. command=(we,ras,cas,cke,odt)
@param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
List elements may be None, those values will not be overwritten
if delay is None will restore default values
@param indx if present, delay only applies to the specified index (delay should be int/long)
@param quiet reduce output
"""
command_offset = 24 + 3
if delay is None:
delay = []
for i in range(5):
if (indx is None) or (i == indx):
delay.append(
vrlg.get_default_field("DLY_CMDA", i + command_offset))
else:
delay.append(None)
if isinstance(delay, (int, long)):
delay = [delay] * 5
if not indx is None:
for i in range(len(delay)):
if (i != indx):
delay[i] = None
if quiet < 2:
print("SET COMMAND ODELAY=" + hexMultiple(delay))
self.axi_set_multiple_delays(
vrlg.LD_DLY_CMDA, command_offset, 0, delay,
"DLY_CMDA") # length will be determined by len(delay)
self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,
0) # set all delays
def axi_set_address_odelay(
self,
delay=None, # input [7:0] delay;
indx=None, # address index
quiet=1):
"""
Set output delays for address lines only
@param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
List elements may be None, those values will not be overwritten
if delay is None will restore default values
@param indx if present, delay only applies to the specified index (delay should be int/long)
@param quiet reduce output
"""
if delay is None:
delay = []
for i in range(0, vrlg.ADDRESS_NUMBER):
if (indx is None) or (i == indx):
delay.append(vrlg.get_default_field("DLY_CMDA", i))
else:
delay.append(None)
if isinstance(delay, (int, long)):
delay = [delay] * vrlg.ADDRESS_NUMBER
if not indx is None:
for i in range(len(delay)):
if (i != indx):
delay[i] = None
if quiet < 2:
print("SET ADDRESS ODELAY=" + hexMultiple(delay))
self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, 0, 0, delay, "DLY_CMDA")
self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,
0) # set all delays
def axi_set_cmd_odelay(self,
delay=None, # input [7:0] delay;
indx=None, # address index
quiet=1):
"""
Set output delays for command lines only. command=(we,ras,cas,cke,odt)
@param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
List elements may be None, those values will not be overwritten
if delay is None will restore default values
@param indx if present, delay only applies to the specified index (delay should be int/long)
@param quiet reduce output
"""
command_offset=24+3
if delay is None:
delay=[]
for i in range(5):
if (indx is None) or (i == indx) :
delay.append(vrlg.get_default_field("DLY_CMDA",i+command_offset))
else:
delay.append(None)
if isinstance(delay,(int,long)):
delay=[delay]*5
if not indx is None:
for i in range(len(delay)):
if (i != indx):
delay[i]=None
if quiet < 2:
print("SET COMMAND ODELAY="+hexMultiple(delay))
self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, command_offset, 0,delay, "DLY_CMDA") # length will be determined by len(delay)
self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0) # set all delays
def axi_set_address_odelay(self,
delay=None, # input [7:0] delay;
indx=None, # address index
quiet=1):
"""
Set output delays for address lines only
@param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
List elements may be None, those values will not be overwritten
if delay is None will restore default values
@param indx if present, delay only applies to the specified index (delay should be int/long)
@param quiet reduce output
"""
if delay is None:
delay=[]
for i in range(0,vrlg.ADDRESS_NUMBER):
if (indx is None) or (i == indx) :
delay.append(vrlg.get_default_field("DLY_CMDA",i))
else:
delay.append(None)
if isinstance(delay,(int,long)):
delay=[delay]*vrlg.ADDRESS_NUMBER
if not indx is None:
for i in range(len(delay)):
if (i != indx):
delay[i]=None
if quiet < 2:
print("SET ADDRESS ODELAY="+hexMultiple(delay))
self.axi_set_multiple_delays(vrlg.LD_DLY_CMDA, 0, 0, delay, "DLY_CMDA")
self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0) # set all delays
def axi_set_dm_odelay (self,
delay=None, # input [7:0] delay;
quiet=1):
"""
Set all DM output delays to the same value
@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
if delay is None will restore default values
@param quiet reduce output
"""
if delay is None:
delay=(vrlg.get_default_field("DLY_LANE0_ODELAY",9),vrlg.get_default_field("DLY_LANE1_ODELAY",9))
if isinstance(delay,(int,long)):
delay=(delay,delay)
if quiet < 2:
print("SET DQM IDELAY="+hexMultiple(delay)) # hexMultiple
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 9, 1, delay[0], "DLY_LANE0_ODELAY")
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 9, 1, delay[1], "DLY_LANE1_ODELAY")
self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0) # set all delays
def axi_set_dqs_idelay(
self,
delay=None, # input [7:0] delay;
quiet=1):
"""
Set all DQs input delays to the same value
@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
if delay is None will restore default values
@param quiet reduce output
"""
if delay is None:
delay = (vrlg.get_default_field("DLY_LANE0_IDELAY", 8),
vrlg.get_default_field("DLY_LANE1_IDELAY", 8))
if isinstance(delay, (int, long)):
delay = (delay, delay)
if quiet < 2:
print("SET DQS IDELAY=" + hexMultiple(delay)) # hexMultiple
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_IDELAY, 8, 1, delay[0],
"DLY_LANE0_IDELAY")
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_IDELAY, 8, 1, delay[1],
"DLY_LANE1_IDELAY")
self.x393_axi_tasks.write_control_register(vrlg.DLY_SET, 0)