def test_extract_type_name(self):
oLine = line.blank_line()
oLine.update_line('variable var1, var2 : integer := -32;')
sExpected = ['integer']
sActual = utils.extract_type_name(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('constant con1 : integer;')
sExpected = ['integer']
sActual = utils.extract_type_name(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line(
'type fbuffer is array (0 to 524288 / 16 - 1) of std_logic_vector(2 downto 0);'
)
sExpected = ['std_logic_vector']
sActual = utils.extract_type_name(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('signal a,')
sExpected = []
sActual = utils.extract_type_name(oLine)
self.assertEqual(sExpected, sActual)
def test_extract_first_keyword(self):
oLine = line.blank_line()
oLine.update_line('MY_LABEL: case (boolean) is')
sExpected = ['case']
sActual = utils.extract_first_keyword(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('if rising_edge(clk) then')
sExpected = ['if']
sActual = utils.extract_first_keyword(oLine)
self.assertEqual(sExpected, sActual)
def test_extract_generics(self):
oLine = line.blank_line()
oLine.update_line('generic( MY_GENERIC: std_logic_vector )')
sExpected = ['MY_GENERIC']
sActual = utils.extract_generics(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('generic(GEN1,GEN2: integer )')
sExpected = ['GEN1', 'GEN2']
sActual = utils.extract_generics(oLine)
self.assertEqual(sExpected, sActual)
def test_extract_label(self):
oLine = line.blank_line()
oLine.update_line(' cp: CPU')
sExpected = ['cp']
sActual = utils.extract_label(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line(' cp : CPU')
sExpected = ['cp']
sActual = utils.extract_label(oLine)
self.assertEqual(sExpected, sActual)
def test_extract_class_name(self):
oLine = line.blank_line()
oLine.update_line('signal s1, s2, s3 : std_logic := \'1\';')
sExpected = ['signal']
sActual = utils.extract_class_name(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('CONSTANT C_MY_CONST : integer := -24;')
sExpected = ['CONSTANT']
sActual = utils.extract_class_name(oLine)
self.assertEqual(sExpected, sActual)
def test_extract_type_name_vhdl_only(self):
oLine = line.blank_line()
oLine.update_line('variable var1, var2 : integer := -32;')
sExpected = ['integer']
sActual = utils.extract_type_name_vhdl_only(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('variable var1, var2 : my_type := -32;')
sExpected = []
sActual = utils.extract_type_name_vhdl_only(oLine)
self.assertEqual(sExpected, sActual)
def test_change_word_w_case(self):
oLine = line.blank_line()
oLine.update_line('RED red green yellow')
sExpected = 'RED blue green yellow'
utils.change_word(oLine, 'red', 'blue', 1)
sActual = oLine.line
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('architecture ARCH of arch is')
sExpected = 'architecture ARCH of ARCH is'
utils.change_word(oLine, 'arch', 'ARCH', 1)
sActual = oLine.line
self.assertEqual(sExpected, sActual)
def test_change_word(self):
oLine = line.blank_line()
oLine.update_line('red blue green yellow')
sExpected = 'blue blue green yellow'
utils.change_word(oLine, 'red', 'blue', 1)
sActual = oLine.line
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('red blue green greenyellow')
sExpected = 'red blue blue greenyellow'
utils.change_word(oLine, 'green', 'blue', 1)
sActual = oLine.line
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('red blue green green,')
sExpected = 'red blue blue green,'
utils.change_word(oLine, 'green', 'blue', 1)
sActual = oLine.line
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('red blue green yellow,')
sExpected = 'red blue green blue,'
utils.change_word(oLine, 'yellow', 'blue', 1)
sActual = oLine.line
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('red blue (green) yellow,')
sExpected = 'red blue (red) yellow,'
utils.change_word(oLine, 'green', 'red', 1)
sActual = oLine.line
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('red blue (green) green,')
sExpected = 'red blue (red) red,'
utils.change_word(oLine, 'green', 'red', 2)
sActual = oLine.line
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('red blue (green) yellow')
sExpected = 'red blue (green) red'
utils.change_word(oLine, 'yellow', 'red', 1)
sActual = oLine.line
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('red blue (green) green;')
sExpected = 'red blue (red) red;'
utils.change_word(oLine, 'green', 'red', 2)
sActual = oLine.line
self.assertEqual(sExpected, sActual)
def test_012(self):
oRule = whitespace.rule_012()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'whitespace')
self.assertEqual(oRule.identifier, '012')
self.assertEqual(oRule.phase, 3)
lExpected = []
dViolation = utils.add_violation(2)
dViolation['remove'] = 3
lExpected.append(dViolation)
dViolation = utils.add_violation(10)
dViolation['remove'] = 1
lExpected.append(dViolation)
# dExpected = [2,10]
# dExpected = [{'lineNumber': 2, 'remove': 3},
# {'lineNumber': 10, 'remove': 1}]
self.oFile.lines.append(line.line(' a <= b;')) #1
self.oFile.lines.append(line.blank_line()) #2
self.oFile.lines.append(line.blank_line()) #3
self.oFile.lines.append(line.blank_line()) #4
self.oFile.lines.append(line.blank_line()) #5
self.oFile.lines.append(line.line(' c <= d;')) #6
self.oFile.lines.append(line.line(' a <= b;')) #7
self.oFile.lines.append(line.blank_line()) #8
self.oFile.lines.append(line.line(' c <= d;')) #9
self.oFile.lines.append(line.blank_line()) #10
self.oFile.lines.append(line.blank_line()) #11
self.oFile.lines.append(line.line(' a <= b;')) #12
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, lExpected)
def test_fix_012(self):
oRule = whitespace.rule_012()
self.assertTrue(oRule)
lFile = utils.read_vhdlfile(sFileName)
oFile = vhdlFile.vhdlFile(lFile)
dExpected = []
oFile.lines.append(line.line(' a <= b;')) #1
oFile.lines.append(line.blank_line()) #2
oFile.lines.append(line.blank_line()) #3
oFile.lines.append(line.blank_line()) #4
oFile.lines.append(line.blank_line()) #5
oFile.lines.append(line.line(' c <= d;')) #6
oFile.lines.append(line.line(' a <= b;')) #7
oFile.lines.append(line.blank_line()) #8
oFile.lines.append(line.line(' c <= d;')) #9
oFile.lines.append(line.blank_line()) #10
oFile.lines.append(line.blank_line()) #11
oFile.lines.append(line.line(' a <= b;')) #12
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
self.assertEqual(oFile.lines[1].line,' a <= b;') #1
self.assertEqual(oFile.lines[2].isBlank,True) #2
self.assertEqual(oFile.lines[3].line,' c <= d;') #3
self.assertEqual(oFile.lines[4].line,' a <= b;') #4
self.assertEqual(oFile.lines[5].isBlank,True) #5
self.assertEqual(oFile.lines[6].line,' c <= d;') #6
self.assertEqual(oFile.lines[7].isBlank,True) #7
self.assertEqual(oFile.lines[8].line,' a <= b;') #8
def test_extract_type_name_from_port(self):
oLine = line.blank_line()
oLine.update_line('PORT( CLK_I : in STD_LOGIC;')
sExpected = ['STD_LOGIC']
sActual = utils.extract_type_name_from_port(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('d : in std_logic_vector(WIDTH-1 downto 0),')
sExpected = ['std_logic_vector']
sActual = utils.extract_type_name_from_port(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('d : in std_logic;')
sExpected = ['std_logic']
sActual = utils.extract_type_name_from_port(oLine)
self.assertEqual(sExpected, sActual)
def _analyze(self, oFile, oLine, iLineNumber):
if oLine.isProcessKeyword and not self.fGroupFound:
self.fGroupFound = True
self.iStartGroupIndex = iLineNumber
if self.fGroupFound:
if oLine.isConstant or oLine.isVariable or oLine.isFileKeyword:
if oLine.insideProcedure or oLine.insideFunction:
self.lGroup.append(line.blank_line())
else:
self.lGroup.append(oLine)
else:
self.lGroup.append(line.blank_line())
if oLine.isProcessBegin and self.fGroupFound:
self.fGroupFound = False
check.identifier_alignment(self, self.iStartGroupIndex,
self.lGroup)
self.lGroup = []
self.iStartGroupIndex = None
def test_is_no_blank_line_after(self):
oFile = vhdlFile.vhdlFile(sFileName)
oFile.lines.append(line.line('Simple line'))
oFile.lines.append(line.blank_line())
oRule = no_blank_check_rule()
self.assertEqual(oRule.violations, [])
oRule.analyze(oFile)
self.assertEqual(oRule.violations, [1])
def test_013(self):
oRule = whitespace.rule_013()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'whitespace')
self.assertEqual(oRule.identifier, '013')
self.assertEqual(oRule.phase, 2)
dExpected = utils.add_violation_list(
[1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, 20])
self.oFile.lines.append(line.line(' if (a = 1)and(b = 0)')) #1
self.oFile.lines.append(line.line(' if (a = 1)nand(b = 0)')) #2
self.oFile.lines.append(line.line(' if (a = 1)or(b = 0)')) #3
self.oFile.lines.append(line.line(' if (a = 1)nor(b = 0)')) #4
self.oFile.lines.append(line.line(' if (a = 1)xor(b = 0)')) #5
self.oFile.lines.append(line.line(' if (a = 1)xnor(b = 0)')) #6
self.oFile.lines.append(line.blank_line()) #7
self.oFile.lines.append(line.line(' if (a = 1) and(b = 0)')) #8
self.oFile.lines.append(line.line(' if (a = 1) nand(b = 0)')) #9
self.oFile.lines.append(line.line(' if (a = 1) or(b = 0)')) #10
self.oFile.lines.append(line.line(' if (a = 1) nor(b = 0)')) #11
self.oFile.lines.append(line.line(' if (a = 1) xor(b = 0)')) #12
self.oFile.lines.append(line.line(' if (a = 1) xnor(b = 0)')) #13
self.oFile.lines.append(line.blank_line()) #14
self.oFile.lines.append(line.line(' if (a = 1)and (b = 0)')) #15
self.oFile.lines.append(line.line(' if (a = 1)nand (b = 0)')) #16
self.oFile.lines.append(line.line(' if (a = 1)or (b = 0)')) #17
self.oFile.lines.append(line.line(' if (a = 1)nor (b = 0)')) #18
self.oFile.lines.append(line.line(' if (a = 1)xor (b = 0)')) #19
self.oFile.lines.append(line.line(' if (a = 1)xnor (b = 0)')) #20
self.oFile.lines.append(line.blank_line()) #21
self.oFile.lines.append(line.line(' if (a = 1) and (b = 0)')) #22
self.oFile.lines.append(line.line(' if (a = 1) nand (b = 0)')) #23
self.oFile.lines.append(line.line(' if (a = 1) or (b = 0)')) #24
self.oFile.lines.append(line.line(' if (a = 1) nor (b = 0)')) #25
self.oFile.lines.append(line.line(' if (a = 1) xor (b = 0)')) #26
self.oFile.lines.append(line.line(' if (a = 1) xnor (b = 0)')) #27
self.oFile.lines.append(line.blank_line()) #28
self.oFile.lines.append(line.line(' std_logic_vector(b = 0)')) #29
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, dExpected)
def insert_line(oFile, iIndex):
'''
Inserts a blank line at iIndex into the file line list.
Parameters:
oFile: (File Object)
iIndex: (integer)
Returns: Nothing
'''
oFile.lines.insert(iIndex, line.blank_line())
def insert_blank_line_below(self, oFile, iLineNumber):
'''
This function inserts a blank line below the line specified by iLineNumber.
Parameters:
self: (rule object)
oFile: (vhdlFile object)
iLineNumber: (integer)
'''
oFile.lines.insert(iLineNumber + 1, line.blank_line())
def insert_blank_line_below(self, oFile, iLineNumber):
'''
This function inserts a blank line below the line specified by iLineNumber.
Parameters:
self: (rule object)
oFile: (vhdlFile object)
iLineNumber: (integer)
'''
oFile.lines.insert(iLineNumber + 1, line.blank_line())
oFile.lines[iLineNumber + 1].insideArchitectureDeclarativeRegion = oFile.lines[iLineNumber].insideArchitectureDeclarativeRegion
def analyze(self, oFile):
lGroup = []
fGroupFound = False
iStartGroupIndex = None
for iLineNumber, oLine in enumerate(oFile.lines):
if oLine.isProcessKeyword and not fGroupFound:
fGroupFound = True
iStartGroupIndex = iLineNumber
if fGroupFound:
if oLine.isConstant or oLine.isVariable or oLine.isFileKeyword:
lGroup.append(oLine)
else:
lGroup.append(line.blank_line())
if oLine.isProcessBegin and fGroupFound:
fGroupFound = False
check.identifier_alignment(self, iStartGroupIndex, lGroup)
check.keyword_alignment(self, iStartGroupIndex, ':', lGroup)
lGroup = []
iStartGroupIndex = None
def test_extract_port_names_from_port_map(self):
oLine = line.blank_line()
oLine.update_line('port map( some_port=>sig,')
sExpected = ['some_port']
sActual = utils.extract_port_names_from_port_map(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('port map (p => s,')
sExpected = ['p']
sActual = utils.extract_port_names_from_port_map(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('map(p100=>s100,')
sExpected = ['p100']
sActual = utils.extract_port_names_from_port_map(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('P1 => S1,')
sExpected = ['P1']
sActual = utils.extract_port_names_from_port_map(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('port1 => S1,')
sExpected = ['port1']
sActual = utils.extract_port_names_from_port_map(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('p1 => s1, p2 => s2)')
sExpected = ['p1', 'p2']
sActual = utils.extract_port_names_from_port_map(oLine)
self.assertEqual(sExpected, sActual)
oLine.update_line(' port_2 (3 downto 0) => w_port_2')
sExpected = ['port_2']
sActual = utils.extract_port_names_from_port_map(oLine)
self.assertEqual(sExpected, sActual)
oLine.update_line(
"PORT_2 => (others => (a => (others => '0'), b => (others => '1')))"
)
sExpected = ['PORT_2', 'b']
sActual = utils.extract_port_names_from_port_map(oLine)
self.assertEqual(sExpected, sActual)
def test_extract_class_identifier_list(self):
oLine = line.blank_line()
oLine.update_line('signal s1, s2, s3 : std_logic := \'1\';')
sExpected = ['s1', 's2', 's3']
sActual = utils.extract_class_identifier_list(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('signal s1, s2, s3')
sExpected = ['s1', 's2', 's3']
sActual = utils.extract_class_identifier_list(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('signal s_x: std_logic;')
sExpected = ['s_x']
sActual = utils.extract_class_identifier_list(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('s1, s2, s3;')
sExpected = ['s1', 's2', 's3']
sActual = utils.extract_class_identifier_list(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('sig;')
sExpected = ['sig']
sActual = utils.extract_class_identifier_list(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('constant C_VALUE : integer;')
sExpected = ['C_VALUE']
sActual = utils.extract_class_identifier_list(oLine)
self.assertEqual(sExpected, sActual)
oLine = line.blank_line()
oLine.update_line('variable var1, var2 : integer := -32;')
sExpected = ['var1', 'var2']
sActual = utils.extract_class_identifier_list(oLine)
self.assertEqual(sExpected, sActual)
def test_012(self):
oRule = whitespace.rule_012()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'whitespace')
self.assertEqual(oRule.identifier, '012')
self.assertEqual(oRule.phase, 3)
dExpected = [2, 10]
self.oFile.lines.append(line.line(' a <= b;')) #1
self.oFile.lines.append(line.blank_line()) #2
self.oFile.lines.append(line.blank_line()) #3
self.oFile.lines.append(line.blank_line()) #4
self.oFile.lines.append(line.blank_line()) #5
self.oFile.lines.append(line.line(' c <= d;')) #6
self.oFile.lines.append(line.line(' a <= b;')) #7
self.oFile.lines.append(line.blank_line()) #8
self.oFile.lines.append(line.line(' c <= d;')) #9
self.oFile.lines.append(line.blank_line()) #10
self.oFile.lines.append(line.blank_line()) #11
self.oFile.lines.append(line.line(' a <= b;')) #12
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, dExpected)
def test_012(self):
oRule = whitespace.rule_012()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'whitespace')
self.assertEqual(oRule.identifier, '012')
self.assertEqual(oRule.phase, 3)
oFile = vhdlFile.vhdlFile(sFileName)
dExpected = [2, 10]
oFile.lines.append(line.line(' a <= b;')) #1
oFile.lines.append(line.blank_line()) #2
oFile.lines.append(line.blank_line()) #3
oFile.lines.append(line.blank_line()) #4
oFile.lines.append(line.blank_line()) #5
oFile.lines.append(line.line(' c <= d;')) #6
oFile.lines.append(line.line(' a <= b;')) #7
oFile.lines.append(line.blank_line()) #8
oFile.lines.append(line.line(' c <= d;')) #9
oFile.lines.append(line.blank_line()) #10
oFile.lines.append(line.blank_line()) #11
oFile.lines.append(line.line(' a <= b;')) #12
oRule.analyze(oFile)
self.assertEqual(oRule.violations, dExpected)
def _fix_violations(self, oFile):
for iLineNumber in self.violations[::-1]:
oFile.lines.insert(iLineNumber, line.blank_line())
def _processFile(self):
dVars = {}
dVars['fFoundProcessBegin'] = False
dVars['SensitivityListFound'] = False
dVars['fProcedureParameterEndDetected'] = False
dVars['fProcedureIsDetected'] = False
dVars['fProcedureBeginDetected'] = False
dVars['fFunctionParameterEndDetected'] = False
dVars['fFunctionIsDetected'] = False
dVars['fFunctionBeginDetected'] = False
dVars['iOpenParenthesis'] = 0
dVars['iCloseParenthesis'] = 0
dVars['iCurrentIndentLevel'] = 0
dVars['iGenerateLevel'] = 0
dVars['iIfLevel'] = 0
dVars['fConstantArray'] = False
dVars['iForLoopLevel'] = 0
oLinePrevious = line.blank_line()
for sLine in self.filecontent:
oLine = line.line(sLine.replace('\t', ' ').rstrip())
update.inside_attributes(dVars, self.lines[-1], oLine)
classify.blank(oLine)
classify.comment(dVars, oLine)
classify.library(oLine)
classify.entity(self, dVars, oLine)
classify.assert_statement(dVars, oLine)
classify.code_tags(dVars, oLine, oLinePrevious)
classify.port(dVars, oLine)
classify.generic(dVars, oLine)
classify.concurrent(dVars, oLine)
classify.architecture(self, dVars, oLine)
classify.package_body(dVars, oLine)
classify.block(self, dVars, oLine)
classify.package(dVars, oLine)
classify.component(dVars, oLine)
classify.signal(dVars, oLine)
classify.constant(dVars, oLine, oLinePrevious)
classify.variable(dVars, oLine)
classify.procedure(dVars, oLine, oLinePrevious)
classify.process(dVars, oLine, self.lines)
classify.generate(dVars, oLine, oLinePrevious)
classify.attribute(dVars, oLine)
classify.file_statement(dVars, oLine)
classify.when(dVars, oLine, oLinePrevious)
classify.with_statement(dVars, oLine)
classify.for_loop(dVars, oLine)
classify.while_loop(dVars, oLine)
classify.if_statement(dVars, oLine)
classify.case(self, dVars, oLine)
classify.function(dVars, oLine)
classify.type_definition(dVars, oLine)
classify.subtype(dVars, oLine)
classify.sequential(dVars, oLine)
classify.variable_assignment(dVars, oLine)
classify.wait(dVars, oLine)
classify.after(dVars, oLine)
# Check instantiation statements
if oLine.insideArchitecture and not oLine.insideProcess and \
not oLine.isConcurrentBegin and \
not oLine.insideComponent and \
not oLine.isGenerateKeyword and \
not oLine.insideFunction and \
not oLine.insideProcedure:
classify.instantiation(dVars, oLine)
# Add line to file
self.lines.append(oLine)
oLinePrevious = oLine
def test_fix_013(self):
oRule = whitespace.rule_013()
lFile = utils.read_vhdlfile(sFileName)
oFile = vhdlFile.vhdlFile(lFile)
dExpected = []
oFile.lines.append(line.line(' if (a = 1)and(b = 0)')) #1
oFile.lines.append(line.line(' if (a = 1)nand(b = 0)')) #2
oFile.lines.append(line.line(' if (a = 1)or(b = 0)')) #3
oFile.lines.append(line.line(' if (a = 1)nor(b = 0)')) #4
oFile.lines.append(line.line(' if (a = 1)xor(b = 0)')) #5
oFile.lines.append(line.line(' if (a = 1)xnor(b = 0)')) #6
oFile.lines.append(line.blank_line()) #7
oFile.lines.append(line.line(' if (a = 1) and(b = 0)')) #8
oFile.lines.append(line.line(' if (a = 1) nand(b = 0)')) #9
oFile.lines.append(line.line(' if (a = 1) or(b = 0)')) #10
oFile.lines.append(line.line(' if (a = 1) nor(b = 0)')) #11
oFile.lines.append(line.line(' if (a = 1) xor(b = 0)')) #12
oFile.lines.append(line.line(' if (a = 1) xnor(b = 0)')) #13
oFile.lines.append(line.blank_line()) #14
oFile.lines.append(line.line(' if (a = 1)and (b = 0)')) #15
oFile.lines.append(line.line(' if (a = 1)nand (b = 0)')) #16
oFile.lines.append(line.line(' if (a = 1)or (b = 0)')) #17
oFile.lines.append(line.line(' if (a = 1)nor (b = 0)')) #18
oFile.lines.append(line.line(' if (a = 1)xor (b = 0)')) #19
oFile.lines.append(line.line(' if (a = 1)xnor (b = 0)')) #20
oFile.lines.append(line.blank_line()) #21
oFile.lines.append(line.line(' if (a = 1) and (b = 0)')) #22
oFile.lines.append(line.line(' if (a = 1) nand (b = 0)')) #23
oFile.lines.append(line.line(' if (a = 1) or (b = 0)')) #24
oFile.lines.append(line.line(' if (a = 1) nor (b = 0)')) #25
oFile.lines.append(line.line(' if (a = 1) xor (b = 0)')) #26
oFile.lines.append(line.line(' if (a = 1) xnor (b = 0)')) #27
oRule.fix(oFile)
oRule.analyze(oFile)
self.assertEqual(oFile.lines[1].line, ' if (a = 1) and (b = 0)') #1
self.assertEqual(oFile.lines[2].line, ' if (a = 1) nand (b = 0)') #2
self.assertEqual(oFile.lines[3].line, ' if (a = 1) or (b = 0)') #3
self.assertEqual(oFile.lines[4].line, ' if (a = 1) nor (b = 0)') #4
self.assertEqual(oFile.lines[5].line, ' if (a = 1) xor (b = 0)') #5
self.assertEqual(oFile.lines[6].line, ' if (a = 1) xnor (b = 0)') #6
self.assertEqual(oFile.lines[8].line, ' if (a = 1) and (b = 0)') #8
self.assertEqual(oFile.lines[9].line, ' if (a = 1) nand (b = 0)') #9
self.assertEqual(oFile.lines[10].line, ' if (a = 1) or (b = 0)') #10
self.assertEqual(oFile.lines[11].line, ' if (a = 1) nor (b = 0)') #11
self.assertEqual(oFile.lines[12].line, ' if (a = 1) xor (b = 0)') #12
self.assertEqual(oFile.lines[13].line,
' if (a = 1) xnor (b = 0)') #13
self.assertEqual(oFile.lines[15].line, ' if (a = 1) and (b = 0)') #15
self.assertEqual(oFile.lines[16].line,
' if (a = 1) nand (b = 0)') #16
self.assertEqual(oFile.lines[17].line, ' if (a = 1) or (b = 0)') #17
self.assertEqual(oFile.lines[18].line, ' if (a = 1) nor (b = 0)') #18
self.assertEqual(oFile.lines[19].line, ' if (a = 1) xor (b = 0)') #19
self.assertEqual(oFile.lines[20].line,
' if (a = 1) xnor (b = 0)') #20
self.assertEqual(oFile.lines[22].line, ' if (a = 1) and (b = 0)') #22
self.assertEqual(oFile.lines[23].line,
' if (a = 1) nand (b = 0)') #23
self.assertEqual(oFile.lines[24].line, ' if (a = 1) or (b = 0)') #24
self.assertEqual(oFile.lines[25].line, ' if (a = 1) nor (b = 0)') #25
self.assertEqual(oFile.lines[26].line, ' if (a = 1) xor (b = 0)') #26
self.assertEqual(oFile.lines[27].line,
' if (a = 1) xnor (b = 0)') #27
self.assertEqual(oRule.violations, dExpected)
