def test_data_core(self):
oRuleList = rule_list.rule_list(oDataCore, oSeverityList)
oRuleList.configure(dLegacyConfig)
oRuleList.fix(7, dLegacyConfig['skip_phase'])
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'data_core.vhd'), lExpected)
self.assertEqual(lExpected, oDataCore.get_lines())
def test_iteration_synth(self):
oRuleList = rule_list.rule_list(oIteration, oSeverityList)
oRuleList.configure(dLegacyConfig)
oRuleList.fix(7, dLegacyConfig['skip_phase'])
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'iteration_synth.vhd'), lExpected)
self.assertEqual(lExpected, oIteration.get_lines())
def test_grp_debouncer(self):
oRuleList = rule_list.rule_list(oGrpDebouncer)
oRuleList.fix(7)
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'grp_debouncer.fixed.vhd'), lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oGrpDebouncer.lines[iLineNumber].line, sLine)
def test_timestamp_vhdl(self):
oRuleList = rule_list.rule_list(oTimestamp)
oRuleList.fix(7)
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'timestamp.fixed.vhdl'), lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oTimestamp.lines[iLineNumber].line, sLine)
def test_pic(self):
oRuleList = rule_list.rule_list(oPIC)
oRuleList.fix(7)
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'PIC.fixed.vhd'), lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oPIC.lines[iLineNumber].line, sLine)
def test_fix_compressed_line(self):
oRuleList = rule_list.rule_list(oFileCompress)
oRuleList.fix(7)
# utils.debug_lines(oFileCompress, 8, 23)
self.assertEqual(oFileCompress.lines[9].line,
' if (A = \'1\' and B = \'1\') then')
self.assertEqual(oFileCompress.lines[10].line, ' X <= \'1\';')
self.assertFalse(oFileCompress.lines[10].isVariableAssignment)
self.assertTrue(oFileCompress.lines[10].isSequential)
self.assertEqual(oFileCompress.lines[11].line,
' elsif (C = \'0\') then')
self.assertEqual(oFileCompress.lines[12].line, ' Y <= \'0\';')
self.assertFalse(oFileCompress.lines[12].isVariableAssignment)
self.assertTrue(oFileCompress.lines[12].isSequential)
self.assertEqual(oFileCompress.lines[13].line, ' else')
self.assertEqual(oFileCompress.lines[14].line, ' W := \'0\';')
self.assertTrue(oFileCompress.lines[14].isVariableAssignment)
self.assertFalse(oFileCompress.lines[14].isSequential)
self.assertFalse(oFileCompress.lines[14].isLastEndIf)
self.assertEqual(oFileCompress.lines[17].line,
' if (A = \'1\' and B = \'1\') then')
self.assertEqual(oFileCompress.lines[18].line, ' X <= \'1\';')
self.assertEqual(oFileCompress.lines[19].line,
' elsif (C = \'0\') then')
self.assertEqual(oFileCompress.lines[20].line, ' Y <= \'0\';')
self.assertEqual(oFileCompress.lines[21].line, ' else')
self.assertEqual(oFileCompress.lines[22].line, ' W <= \'0\';')
def test_board_cpu(self):
oRuleList = rule_list.rule_list(oBoardCpu, oSeverityList)
oRuleList.configure(dLegacyConfig)
oRuleList.fix(7, dLegacyConfig['skip_phase'])
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'Board_cpu.vhd'), lExpected)
self.assertEqual(lExpected, oBoardCpu.get_lines())
def test_framebuffer(self):
oRuleList = rule_list.rule_list(oFrameBuffer)
oRuleList.configure(dLegacyConfig)
oRuleList.fix(7, dLegacyConfig['skip_phase'])
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'FrameBuffer2.vhd'), lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oFrameBuffer.lines[iLineNumber].line, sLine)
def test_vga_top(self):
oRuleList = rule_list.rule_list(oVgatop, oSeverityList)
oRuleList.configure(dLegacyConfig)
oRuleList.fix(7, dLegacyConfig['skip_phase'])
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__), 'VGA_Top.vhd'),
lExpected)
self.assertEqual(lExpected, oVgatop.get_lines())
def test_spi_slave(self):
oRuleList = rule_list.rule_list(oSpiSlave, oSeverityList)
oRuleList.configure(oConfig)
oRuleList.fix()
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'spi_slave.fixed.vhd'), lExpected)
self.assertEqual(lExpected, oSpiSlave.get_lines())
def test_iteration_synth(self):
oRuleList = rule_list.rule_list(oIteration)
oRuleList.configure(dLegacyConfig)
oRuleList.fix(7, dLegacyConfig['skip_phase'])
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'iteration_synth.vhd'), lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oIteration.lines[iLineNumber].line, sLine)
def test_identifier(self):
oRuleList = rule_list.rule_list(oIdentifier)
oRuleList.fix(7)
# utils.debug_lines(oIdentifier, 1, 20)
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'identifier_alignment_input.fixed.vhd'), lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oIdentifier.lines[iLineNumber].line, sLine)
def test_freqdiv(self):
oRuleList = rule_list.rule_list(oFreqDiv, oSeverityList)
oRuleList.configure(dLegacyConfig)
oRuleList.fix(7, dLegacyConfig['skip_phase'])
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__), 'FreqDiv.vhd'),
lExpected)
self.assertEqual(lExpected, oFreqDiv.get_lines())
def test_rule_007_library(self):
oRuleList = rule_list.rule_list(oFileLibrary)
oRuleList.check_rules()
iExpectedFailures = 1
iFailures = 0
for oRule in oRuleList.rules:
iFailures += len(oRule.violations)
self.assertEqual(iFailures, iExpectedFailures)
def test_rule_001(self):
oRuleList = rule_list.rule_list(oFileLibrary)
oRuleList.fix(7)
oRuleList.check_rules()
self.assertEqual(oFileLibrary.lines[4].indentLevel, 1)
self.assertEqual(oFileLibrary.lines[8].indentLevel, 1)
self.assertEqual(oFileLibrary.lines[4].line, ' -- Comment 1')
self.assertEqual(oFileLibrary.lines[8].line, ' -- Comment 1')
oRuleList = rule_list.rule_list(oFileLibrary)
oRuleList.check_rules()
iExpectedFailures = 0
iFailures = 0
for oRule in oRuleList.rules:
iFailures += len(oRule.violations)
self.assertEqual(iFailures, iExpectedFailures)
def test_grp_debouncer(self):
oRuleList = rule_list.rule_list(oGrpDebouncer, oSeverityList)
oRuleList.configure(oConfig)
oRuleList.fix()
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'grp_debouncer.fixed.vhd'), lExpected)
self.assertEqual(lExpected, oGrpDebouncer.get_lines())
def test_synchronizer(self):
oRuleList = rule_list.rule_list(oSynchronizer, oSeverityList)
oRuleList.configure(dLegacyConfig)
oRuleList.fix(7, dLegacyConfig['skip_phase'])
lExpected = ['']
utils.read_file(
os.path.join(os.path.dirname(__file__), 'Synchronizer.vhd'),
lExpected)
self.assertEqual(lExpected, oSynchronizer.get_lines())
def test_timestamp_vhdl(self):
oRuleList = rule_list.rule_list(oTimestamp, oSeverityList)
oRuleList.configure(dLegacyConfig)
oRuleList.fix(7, dLegacyConfig['skip_phase'])
lExpected = ['']
utils.read_file(
os.path.join(os.path.dirname(__file__), 'timestamp.vhdl'),
lExpected)
self.assertEqual(lExpected, oTimestamp.get_lines())
def test_baudgen(self):
oRuleList = rule_list.rule_list(oBaudGen, oSeverityList)
oRuleList.configure(oConfig)
oRuleList.fix(7, oConfig.dConfig['skip_phase'])
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__), 'BaudGen.vhd'),
lExpected,
bStrip=False)
self.assertEqual(lExpected, oBaudGen.get_lines())
def test_synchronizer(self):
oRuleList = rule_list.rule_list(oSynchronizer)
oRuleList.configure(dConfig)
oRuleList.fix()
lExpected = ['']
utils.read_file(
os.path.join(os.path.dirname(__file__), 'Synchronizer.fixed.vhd'),
lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oSynchronizer.lines[iLineNumber].line, sLine)
def test_framebuffer(self):
oRuleList = rule_list.rule_list(oFrameBuffer, oSeverityList)
oRuleList.configure(oConfig)
oRuleList.fix(7, oConfig.dConfig['skip_phase'])
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),
'FrameBuffer2.vhd'),
lExpected,
bStrip=False)
self.assertEqual(lExpected, oFrameBuffer.get_lines())
def test_board_cpu(self):
oRuleList = rule_list.rule_list(oBoardCpu)
oRuleList.configure(dConfig)
oRuleList.fix()
lExpected = ['']
utils.read_file(
os.path.join(os.path.dirname(__file__), 'Board_cpu.fixed.vhd'),
lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oBoardCpu.lines[iLineNumber].line, sLine)
def test_vga_top(self):
oRuleList = rule_list.rule_list(oVgatop)
oRuleList.configure(dConfig)
oRuleList.fix()
lExpected = ['']
utils.read_file(
os.path.join(os.path.dirname(__file__), 'VGA_Top.fixed.vhd'),
lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oVgatop.lines[iLineNumber].line, sLine)
def test_data_core(self):
oRuleList = rule_list.rule_list(oDataCore)
oRuleList.configure(dConfig)
oRuleList.fix()
lExpected = ['']
utils.read_file(
os.path.join(os.path.dirname(__file__), 'data_core.fixed.vhd'),
lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oDataCore.lines[iLineNumber].line, sLine)
def test_pic(self):
oRuleList = rule_list.rule_list(oPIC, oSeverityList)
oRuleList.configure(dConfig)
oRuleList.fix()
lExpected = ['']
utils.read_file(
os.path.join(os.path.dirname(__file__), 'PIC.fixed.vhd'),
lExpected)
self.assertEqual(lExpected, oPIC.get_lines())
def test_extract_violation_dictionary_w_all_phases_enabled(self):
self.maxDiff = None
lFile = []
utils.read_file('vsg/tests/styles/code_examples/spi_master.vhd', lFile)
oFile = vhdlFile.vhdlFile(lFile)
oFile.set_indent_map(dIndentMap)
oRules = rule_list.rule_list(oFile, oSeverityList)
oRules.check_rules(True)
with open('vsg/tests/rule_list/extract_violation_dictionary_w_all_phases_enabled.json') as jsonFile:
dExpected = json.load(jsonFile)
self.assertEqual(dExpected, oRules.extract_violation_dictionary())
def test_baudgen(self):
oRuleList = rule_list.rule_list(oBaudGen)
dConfiguration = {}
dConfiguration['rule'] = {}
dConfiguration['rule']['global'] = {}
dConfiguration['rule']['global']['separate_generic_port_alignment'] = False
oRuleList.configure(dConfiguration)
oRuleList.fix(7)
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'BaudGen.fixed.vhd'), lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oBaudGen.lines[iLineNumber].line, sLine)
def test_baudgen(self):
oRuleList = rule_list.rule_list(oBaudGen, oSeverityList)
oRuleList.configure(oConfig)
oRuleList.fix()
lExpected = ['']
utils.read_file(
os.path.join(os.path.dirname(__file__), 'BaudGen.fixed.vhd'),
lExpected)
self.assertEqual(lExpected, oBaudGen.get_lines())
def test_data_core(self):
oRuleList = rule_list.rule_list(oDataCore)
dConfiguration = {}
dConfiguration['rule'] = {}
dConfiguration['rule']['global'] = {}
dConfiguration['rule']['global']['compact_alignment'] = False
oRuleList.configure(dConfiguration)
oRuleList.fix(7)
lExpected = ['']
utils.read_file(os.path.join(os.path.dirname(__file__),'data_core.fixed.vhd'), lExpected)
for iLineNumber, sLine in enumerate(lExpected):
self.assertEqual(oDataCore.lines[iLineNumber].line, sLine)
def test_framebuffer(self):
oRuleList = rule_list.rule_list(oFrameBuffer, oSeverityList)
oRuleList.configure(dConfig)
oRuleList.fix()
lExpected = ['']
utils.read_file(
os.path.join(os.path.dirname(__file__), 'FrameBuffer2.fixed.vhd'),
lExpected)
self.assertEqual(lExpected, oFrameBuffer.get_lines())
