def test_fix_rule_015_default(self):
oRule = signal.rule_015()
oRule.fix(self.oFile)
oRule.analyze(self.oFile)
self.assertEqual(self.oFile.lines[5].line, ' signal sig1 : std_logic;')
self.assertTrue(self.oFile.lines[5].isSignal)
self.assertTrue(self.oFile.lines[5].insideSignal)
self.assertTrue(self.oFile.lines[5].isEndSignal)
self.assertFalse(self.oFile.lines[5].isComment)
self.assertFalse(self.oFile.lines[5].hasComment)
self.assertFalse(self.oFile.lines[5].hasInlineComment)
self.assertEqual(self.oFile.lines[5].commentColumn, None)
self.assertFalse(self.oFile.lines[5].isBlank)
self.assertEqual(self.oFile.lines[6].line, ' signal sig2 : std_logic;')
self.assertEqual(self.oFile.lines[7].line, ' signal sig3 : std_logic;')
self.assertEqual(self.oFile.lines[8].line, ' signal sig4 : std_logic;')
self.assertEqual(self.oFile.lines[9].line, ' signal sig5 : std_logic;')
self.assertEqual(self.oFile.lines[10].line, ' signal sig6 : std_logic;')
self.assertEqual(self.oFile.lines[12].line, ' signal siga : std_logic; -- This is a comment')
self.assertFalse(self.oFile.lines[12].isComment)
self.assertTrue(self.oFile.lines[12].hasComment)
self.assertTrue(self.oFile.lines[12].hasInlineComment)
self.assertEqual(self.oFile.lines[12].commentColumn, 27)
self.assertEqual(self.oFile.lines[13].line, ' signal sigb : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[14].line, ' signal sigc : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[15].line, ' signal sigd : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[16].line, ' signal sige : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[17].line, ' signal sigf : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[83].line, ' signal foo : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);')
self.assertEqual(self.oFile.lines[84].line, ' signal bar : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);')
self.assertEqual(self.oFile.lines[85].line, ' signal mine : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);')
self.assertEqual(oRule.violations, [])
def test_rule_015_consecutive_1(self):
oRule = signal.rule_015()
oRule.consecutive = 1
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '015')
lExpected = []
dViolation = utils.add_violation(5)
dViolation['endLine'] = 6
dViolation['line'] = ' signal sig1, sig2, sig3, sig4, sig5, sig6 : std_logic;'
lExpected.append(dViolation)
dViolation = utils.add_violation(8)
dViolation['endLine'] = 13
dViolation['line'] = ' signal siga, sigb, sigc, sigd, sige, sigf : std_logic; -- This is a comment'
lExpected.append(dViolation)
dViolation = utils.add_violation(40)
dViolation['endLine'] = 40
dViolation['line'] = ' signal sig1, sig2 : std_logic;'
lExpected.append(dViolation)
dViolation = utils.add_violation(42)
dViolation['endLine'] = 43
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(45)
dViolation['endLine'] = 47
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(49)
dViolation['endLine'] = 52
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(54)
dViolation['endLine'] = 58
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(60)
dViolation['endLine'] = 65
dViolation['line'] = ' signal sig1 , sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(67)
dViolation['endLine'] = 73
dViolation['line'] = ' signal sig1 , sig2 : std_logic ;'
lExpected.append(dViolation)
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, lExpected)
def test_fix_rule_015(self):
oRule = signal.rule_015()
self.maxDiff = None
oRule.fix(self.oFile)
lActual = self.oFile.get_lines()
self.assertEqual(lExpected, lActual)
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, [])
def test_fix_rule_015_default_consecutive_1(self):
oRule = signal.rule_015()
oRule.consecutive = 1
oRule.fix(self.oFile)
oRule.analyze(self.oFile)
self.assertEqual(self.oFile.lines[5].line, ' signal sig1 : std_logic;')
self.assertEqual(self.oFile.lines[6].line, ' signal sig2 : std_logic;')
self.assertEqual(self.oFile.lines[7].line, ' signal sig3 : std_logic;')
self.assertEqual(self.oFile.lines[8].line, ' signal sig4 : std_logic;')
self.assertEqual(self.oFile.lines[9].line, ' signal sig5 : std_logic;')
self.assertEqual(self.oFile.lines[10].line, ' signal sig6 : std_logic;')
self.assertEqual(self.oFile.lines[12].line, ' signal siga : std_logic; -- This is a comment')
self.assertFalse(self.oFile.lines[12].isComment)
self.assertTrue(self.oFile.lines[12].hasComment)
self.assertTrue(self.oFile.lines[12].hasInlineComment)
self.assertEqual(self.oFile.lines[12].commentColumn, 27)
self.assertEqual(self.oFile.lines[13].line, ' signal sigb : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[14].line, ' signal sigc : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[15].line, ' signal sigd : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[16].line, ' signal sige : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[17].line, ' signal sigf : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[44].line, ' signal sig1 : std_logic;')
self.assertEqual(self.oFile.lines[45].line, ' signal sig2 : std_logic;')
self.assertEqual(self.oFile.lines[47].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[48].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[50].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[51].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[53].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[54].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[56].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[57].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[59].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[60].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[62].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[63].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[65].line, ' signal sig1 : std_logic; -- Comma, should not induce a failure')
self.assertEqual(self.oFile.lines[66].line, ' signal sig2 : std_logic; -- Comma, should not induce a failure')
self.assertEqual(self.oFile.lines[70].line, ' signal foo : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);')
self.assertEqual(self.oFile.lines[71].line, ' signal bar : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);')
self.assertEqual(self.oFile.lines[72].line, ' signal mine : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);')
self.assertEqual(oRule.violations, [])
def test_rule_015(self):
oRule = signal.rule_015()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '015')
lExpected = [5, 8, 79, 81, 82]
oRule.analyze(self.oFile)
self.assertEqual(
lExpected,
utils.extract_violation_lines_from_violation_object(
oRule.violations))
def test_rule_015_consecutive_1(self):
oRule = signal.rule_015()
oRule.consecutive = 1
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '015')
dExpected = [{
'endLine': 6,
'line':
' signal sig1, sig2, sig3, sig4, sig5, sig6 : std_logic;',
'lineNumber': 5
}, {
'endLine': 13,
'line':
' signal siga, sigb, sigc, sigd, sige, sigf : std_logic; -- This is a comment',
'lineNumber': 8
}, {
'endLine': 40,
'line': ' signal sig1, sig2 : std_logic;',
'lineNumber': 40
}, {
'endLine': 43,
'line': ' signal sig1, sig2 : std_logic ;',
'lineNumber': 42
}, {
'endLine': 47,
'line': ' signal sig1, sig2 : std_logic ;',
'lineNumber': 45
}, {
'endLine': 52,
'line': ' signal sig1, sig2 : std_logic ;',
'lineNumber': 49
}, {
'endLine': 58,
'line': ' signal sig1, sig2 : std_logic ;',
'lineNumber': 54
}, {
'endLine': 65,
'line': ' signal sig1 , sig2 : std_logic ;',
'lineNumber': 60
}, {
'endLine': 73,
'line': ' signal sig1 , sig2 : std_logic ;',
'lineNumber': 67
}]
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, dExpected)
def test_fix_rule_015_default_consecutive_1(self):
oRule = signal.rule_015()
oRule.consecutive = 1
oRule.fix(self.oFile)
oRule.analyze(self.oFile)
self.assertEqual(self.oFile.lines[5].line, ' signal sig1 : std_logic;')
self.assertEqual(self.oFile.lines[6].line, ' signal sig2 : std_logic;')
self.assertEqual(self.oFile.lines[7].line, ' signal sig3 : std_logic;')
self.assertEqual(self.oFile.lines[8].line, ' signal sig4 : std_logic;')
self.assertEqual(self.oFile.lines[9].line, ' signal sig5 : std_logic;')
self.assertEqual(self.oFile.lines[10].line, ' signal sig6 : std_logic;')
self.assertEqual(self.oFile.lines[12].line, ' signal siga : std_logic; -- This is a comment')
self.assertFalse(self.oFile.lines[12].isComment)
self.assertTrue(self.oFile.lines[12].hasComment)
self.assertTrue(self.oFile.lines[12].hasInlineComment)
self.assertEqual(self.oFile.lines[12].commentColumn, 27)
self.assertEqual(self.oFile.lines[13].line, ' signal sigb : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[14].line, ' signal sigc : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[15].line, ' signal sigd : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[16].line, ' signal sige : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[17].line, ' signal sigf : std_logic; -- This is a comment')
self.assertEqual(self.oFile.lines[44].line, ' signal sig1 : std_logic;')
self.assertEqual(self.oFile.lines[45].line, ' signal sig2 : std_logic;')
self.assertEqual(self.oFile.lines[47].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[48].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[50].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[51].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[53].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[54].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[56].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[57].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[59].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[60].line, ' signal sig2 : std_logic ;')
self.assertEqual(self.oFile.lines[62].line, ' signal sig1 : std_logic ;')
self.assertEqual(self.oFile.lines[63].line, ' signal sig2 : std_logic ;')
self.assertEqual(oRule.violations, [])
def test_rule_015_consecutive_default(self):
oRule = signal.rule_015()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '015')
dExpected = [{
'endLine': 6,
'line':
' signal sig1, sig2, sig3, sig4, sig5, sig6 : std_logic;',
'lineNumber': 5
}, {
'endLine': 13,
'line':
' signal siga, sigb, sigc, sigd, sige, sigf : std_logic; -- This is a comment',
'lineNumber': 8
}]
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, dExpected)
def test_rule_015_consecutive_default(self):
oRule = signal.rule_015()
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '015')
lExpected = []
dViolation = utils.add_violation(5)
dViolation['endLine'] = 6
dViolation['line'] = ' signal sig1, sig2, sig3, sig4, sig5, sig6 : std_logic;'
lExpected.append(dViolation)
dViolation = utils.add_violation(8)
dViolation['endLine'] = 13
dViolation['line'] = ' signal siga, sigb, sigc, sigd, sige, sigf : std_logic; -- This is a comment'
lExpected.append(dViolation)
dViolation = utils.add_violation(79)
dViolation['endLine'] = 79
dViolation['line'] = ' signal foo, bar, mine : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);'
lExpected.append(dViolation)
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, lExpected)
def test_rule_015_consecutive_1(self):
oRule = signal.rule_015()
oRule.consecutive = 1
self.assertTrue(oRule)
self.assertEqual(oRule.name, 'signal')
self.assertEqual(oRule.identifier, '015')
lExpected = []
dViolation = utils.add_violation(5)
dViolation['endLine'] = 6
dViolation['line'] = ' signal sig1, sig2, sig3, sig4, sig5, sig6 : std_logic;'
lExpected.append(dViolation)
dViolation = utils.add_violation(8)
dViolation['endLine'] = 13
dViolation['line'] = ' signal siga, sigb, sigc, sigd, sige, sigf : std_logic; -- This is a comment'
lExpected.append(dViolation)
dViolation = utils.add_violation(40)
dViolation['endLine'] = 40
dViolation['line'] = ' signal sig1, sig2 : std_logic;'
lExpected.append(dViolation)
dViolation = utils.add_violation(42)
dViolation['endLine'] = 43
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(45)
dViolation['endLine'] = 47
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(49)
dViolation['endLine'] = 52
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(54)
dViolation['endLine'] = 58
dViolation['line'] = ' signal sig1, sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(60)
dViolation['endLine'] = 65
dViolation['line'] = ' signal sig1 , sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(67)
dViolation['endLine'] = 73
dViolation['line'] = ' signal sig1 , sig2 : std_logic ;'
lExpected.append(dViolation)
dViolation = utils.add_violation(75)
dViolation['endLine'] = 75
dViolation['line'] = ' signal sig1, sig2 : std_logic; -- Comma, should not induce a failure'
lExpected.append(dViolation)
dViolation = utils.add_violation(79)
dViolation['endLine'] = 79
dViolation['line'] = ' signal foo, bar, mine : std_logic_vector(maximum(G_A, G_B) + maximum(C_A, C_B)-1 downto 0);'
lExpected.append(dViolation)
oRule.analyze(self.oFile)
self.assertEqual(oRule.violations, lExpected)
