def test_compile_project_verilog_extra_flags(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v", "lib", file_type="verilog")
source_file.set_compile_option("activehdl.vlog_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-lc',
library_cfg,
'custom',
'flags',
'-work',
'lib',
'file.v',
'-l', 'lib'],
env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, check_output):
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("activehdl.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'],
env=simif.get_env())
def test_compile_project_system_verilog(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.sv", "")
project.add_source_file("file.sv", "lib", file_type="systemverilog")
simif.compile_project(project)
process.assert_any_call(
[join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
process.assert_called_with(
[join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
check_output.assert_called_once_with(
[
join("prefix", "vlog"),
"-quiet",
"-lc",
library_cfg,
"-work",
"lib",
"file.sv",
"-l",
"lib",
],
env=simif.get_env(),
)
def test_compile_project_verilog_define(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+define+defname=defval'],
env=simif.get_env())
def test_compile_project_vhdl(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
run_command.assert_called_once_with(
[join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'-2008',
'-work',
'lib',
'file.vhd'],
env=simif.get_env())
def test_compile_project_verilog_include(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", include_dirs=["include"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+incdir+include'],
env=simif.get_env())
def test_compile_project_vhdl_2002(self, process, check_output):
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("2002"))
simif.compile_project(project)
process.assert_any_call(
[join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
process.assert_called_with(
[join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
check_output.assert_called_once_with(
[
join("prefix", "vcom"),
"-quiet",
"-j",
self.output_path,
"-2002",
"-work",
"lib",
"file.vhd",
],
env=simif.get_env(),
)
def test_compile_project_verilog(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib'])
def test_compile_project_verilog(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog")
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib'])
def test_compile_project_vhdl(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd", "lib", file_type="vhdl")
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with(
[join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'-2008',
'-work',
'lib',
'file.vhd'])
def test_compile_project_verilog_define(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+define+defname=defval'],
env=simif.get_env())
def test_compile_project_vhdl_extra_flags(self, process, check_output):
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("activehdl.vcom_flags", ["custom", "flags"])
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'],
env=simif.get_env())
def test_compile_project_verilog_define(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'-work',
'lib',
'file.v',
'-l', 'lib',
'+define+defname=defval'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_vhdl_extra_flags(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("activehdl.vcom_flags", ["custom", "flags"])
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'])
def test_compile_project_vhdl_extra_flags(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
source_file.set_compile_option("activehdl.vcom_flags", ["custom", "flags"])
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vcom'),
'-quiet',
'-j',
self.output_path,
'custom',
'flags',
'-2008',
'-work',
'lib',
'file.vhd'],
simif._compile_output_consumer) # pylint: disable=protected-access
def test_compile_project_verilog_extra_flags(self, process, run_command):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
library_cfg=library_cfg)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v", "lib", file_type="verilog")
source_file.set_compile_option("activehdl.vlog_flags", ["custom", "flags"])
simif.compile_project(project, vhdl_standard="2008")
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
run_command.assert_called_once_with([join('prefix', 'vlog'),
'-quiet',
'-sv2k12',
'-lc',
library_cfg,
'custom',
'flags',
'-work',
'lib',
'file.v',
'-l', 'lib'])
def test_compile_project_vhdl_93(self, process, check_output):
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.vhd", "")
project.add_source_file("file.vhd",
"lib",
file_type="vhdl",
vhdl_standard=VHDL.standard("93"))
simif.compile_project(project)
process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env())
check_output.assert_called_once_with([
join('prefix', 'vcom'), '-quiet', '-j', self.output_path, '-93',
'-work', 'lib', 'file.vhd'
],
env=simif.get_env())
def test_compile_project_verilog_extra_flags(self, process, check_output):
library_cfg = join(self.output_path, "library.cfg")
simif = ActiveHDLInterface(prefix="prefix",
output_path=self.output_path)
project = Project()
project.add_library("lib", "lib_path")
write_file("file.v", "")
source_file = project.add_source_file("file.v",
"lib",
file_type="verilog")
source_file.set_compile_option("activehdl.vlog_flags",
["custom", "flags"])
simif.compile_project(project)
process.assert_any_call(
[join("prefix", "vlib"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
process.assert_called_with(
[join("prefix", "vmap"), "lib", "lib_path"],
cwd=self.output_path,
env=simif.get_env(),
)
check_output.assert_called_once_with(
[
join("prefix", "vlog"),
"-quiet",
"-lc",
library_cfg,
"custom",
"flags",
"-work",
"lib",
"file.v",
"-l",
"lib",
],
env=simif.get_env(),
)
