def _create_entity():
"""
Helper function to create a VHDLEntity
"""
data_width = VHDLInterfaceElement("data_width",
VHDLSubtypeIndication.parse("natural := 16"))
clk = VHDLInterfaceElement("clk",
VHDLSubtypeIndication.parse("std_logic"),
"in")
data = VHDLInterfaceElement("data",
VHDLSubtypeIndication.parse("std_logic_vector(data_width-1 downto 0)"),
"out")
entity = VHDLEntity(identifier="name",
generics=[data_width],
ports=[clk, data])
return entity
def test_converting_interface_element_to_string(self):
iface_element = VHDLInterfaceElement("identifier",
VHDLSubtypeIndication.parse("integer"),
"in",
"0")
self.assertEqual(str(iface_element),
"identifier : in integer := 0")
iface_element = VHDLInterfaceElement("identifier",
VHDLSubtypeIndication.parse("integer"),
"in")
self.assertEqual(str(iface_element),
"identifier : in integer")
iface_element = VHDLInterfaceElement("identifier",
VHDLSubtypeIndication.parse("integer"))
self.assertEqual(str(iface_element),
"identifier : integer")